Process for forming self-aligned complementary source/drain regions for MOS transistors

Claim 2

In the fabrication of complementary metal-oxide-semiconductor (CMOS) transistors on a silicon substrate, the improvement comprising the steps of: subjecting said substrate to a doping step so as to form first source and drain regions of a first conductivity type for first transistors; growing an insulative layer on said substrate such that a thicker insulative oxide layer is formed over said first source and drain regions than over locations for second source and drain regions for second transistors; subjecting said substrate to ion implantation with ions of a second conductivity type at an energy level selected such that said thicker insulative layer substantially blocks said ions of said second conductivity type, thereby forming said second source and drain regions, whereby CMOS transistors are formed in said substrate.

Claim 3

The improvement defined by claim 1 wherein gate members for said first transistors are doped with said first conductivity type dopant when said first source and drain regions are formed.

Claim 4

The improvement defined by claim 2 wherein gate members for said second transistors are implanted with said ions of said second conductivity type when said second source and drain regions are formed.

Claim 5

The improvement defined by claim 1 wherein gate member for said first and second transistors are covered with silicon nitride when said insulative layer is grown.

Claim 6

In the fabrication of complementary metal-oxide-semiconductor (CMOS) transistors on a silicon substrate, where first predetermined regions are used for first transistors of a first conductivity type and second predetermined regions are used for second transistors of a second conductivity type, the improvement comprising the steps of: covering said second predetermined regions while leaving said first predetermined regions exposed; subjecting said substrate to a doping step with a dopant of a first conductivity type such that first source and drain regions are formed for said first transistors; growing an insulative layer on said substrate such that a thicker layer is formed over said first source and drain regions than over at least portions of said second predetermined regions, subjecting said substrate to ion implantation with ions of a second conductivity type at an energy level selected such that said thicker layer substantially blocks said ions of said second conductivity type, while allowing said ions to penetrate said layer over said second predetermined regions, thereby forming second source and drain regions for said second transistors, whereby CMOS transistors are formed in said substrate.

Claim 7

In the fabrication of complementary metal-oxide-semiconductor (CMOS) transistors on a silicon substrate, where first predetermined regions are used for first transistors of a first conductivity type and second predetermined regions are used for second transistors of a second conductivity type, the improvement comprising the steps of: covering said second predetermined regions while leaving said first predetermined regions exposed; subjecting said substrate to a doping step with a dopant of a first conductivity type such that first source and drain regions are formed for said first transistors; growing an insulative layer on said substrate such that a thicker layer is formed over said first source and drain regions than over at least portions of said second predetermined regions, subjecting said substrate to ion implantation with ions of a second conductivity type at an energy level selected such that said thicker layer substantially blocks said ions of said second conductivity type, while allowing said ions to penetrate said layer over said second predetermined regions, thereby forming second source and drain regions for said second transistors, whereby CMOS transistors are formed in said substrate.

Claim 8

The improvement defined by claim 5 wherein gate members for said first transistors are doped with said first conductivity dopant when said first source and drain regions are formed.

Claim 9

The improvement defined by claim 6 wherein gate members for said second transistors are implanted with said ions of said second conductivity type when said second source and drain regions are formed.

Claim 10

The improvement defined by claim 7 wherein said insulative layer is a silicon dioxide layer.

Claim 11

The improvement defined by claim 5 wherein gate members for said first and second transistors are covered with silicon nitride when said insulative layer is grown.

Claim 12

The improvement defined by claim 9 wherein said insulative layer is silicon dioxide.

Claim 13

In a process for fabricating complementary metal-oxide-semiconductor (CMOS) transistors on a silicon substrate, the improvement comprising the steps of: forming first and second polysilicon gate members insulated from said substrate; forming first source and drain regions of a first conductivity type in general alignment with said first gate members; growing an oxide layer on said substrate such that a thicker oxide layer is formed over said first source and drain regions than is grown adjacent to said second gate members since said substrate is more heavily doped at said first source and drain regions; subjecting said substrate to ion implantation with an ion of the second conductivity type at an energy level selected such that said thicker oxide layer substantially blocks said ions of said second conductivity type, thereby forming second source and drain regions of said second conductivity type in general alignment with said second gate members, whereby CMOS transistors are formed.

Claim 14

In a process for fabricating complementary metal-oxide-semiconductor (CMOS) transistors on a silicon substrate, the improvement comprising the steps of: forming first and second polysilicon gate members insulated from said substrate; forming first source and drain regions of a first conductivity type in general alignment with said first gate members; growing an oxide layer on said substrate such that a thicker oxide layer is formed over said first source and drain regions than is grown adjacent to said second gate members since said substrate is more heavily doped at said first source and drain regions; subjecting said substrate to ion implantation with an ion of the second conductivity type at an energy level selected such that said thicker oxide layer substantially blocks said ions of said second conductivity type, thereby forming second source and drain regions of said second conductivity type in general alignment with said second gate members, whereby CMOS transistors are formed.

Claim 15

The improvement defined by claim 11 including, after forming of said gate members, the steps of: forming a photoresist layer over said substrate, removing portions of said photoresist layer so as to expose sites for said first source and drain regions.

Claim 16

The improvement defined by claim 12 wherein said first gate members are doped to said first conductivity type when said first source and drain regions are formed.

Claim 17

The improvement defined by claim 13 wherein said second gate members are doped to said second conductivity type by said ions when said second source and drain regions are formed.

Claim 18

The improvement defined by claim 11 wherein said first and second gate members are formed from a doped layer of polysilicon and include overlying silicon nitride members, and wherein said silicon nitride members prevent growth of said oxide layer on said gate members.

Claim 19

The improvement defined by claim 11 wherein said ions are weighted with other atoms.

Claim 20

The improvement defined by claim 16 wherein said ions are boron ions weighted with fluorine.