US4509067A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit devices with protective means against overvoltages
Assignee: Toshiba Corp
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Filing: 1982-03-03
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Granted: 1985-04-02
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Expires: 2002-03-03
Abstract
Abstract An additional N + region is provided in a P type substrate adjacent to a protective N + resistor region with an insulating layer and metal layer interposed between the N + region and the N + resistor region. The N + resistor region, the oxide layer, the polysilicon layer and N + region constitute an MOS transistor, respectively corresponding to a drain region, a gate insulating layer, a gate electrode and a source region of the MOS transistor. When a very high excessive voltage that otherwise would destroy the PN junction between the substrate and the resistor region is applied to the input terminal, the MOS transistor is rendered conductive and the excessive voltage is absorbed.
Inventors
- 👤 Kenji Minami
- 👤 Masaru Katagiri
- 👤 Hideo Noguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:51
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D48/00; H10D48/30; H10D84/00; H10D84/201; H10D84/204; H10D84/209
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
236 words
A semiconductor integrated circuit comprising: a semiconductor substrate of a first conductivity type of a given impurity concentration; an active semiconductor element formed in said substrate; a protective resistor region of a second conductivity type opposite to said first conductivity type formed in the surface of the substrate, said protective resistor region being electrically connected to said active element; an input contact portion in said resistor region for connecting an input signal to said resistor region; and protective means including a metal oxide semiconductor field effect transistor formed to substantially surround said resistor region and electrically connected to said resistor region for being rendered conductive only by excessive voltage surges applied to said input contact portion of said resistor region and for absorbing such excess voltage surges and thereby protecting said active element; wherein said metal oxide semiconductor field effect transistor is comprised of said resistor region; a second conductivity type region in the semiconductor substrate substantially surrounding at least the input contact portion of said resistor region; an insulating layer formed adjacent to and insulating said second conductivity type region from said resistor region; a conducting layer formed at least in part on the insulating layer and extending over at least a part of said resistor region; and a channel stopper region of said first conductivity type having a higher impurity concentration than said substrate and located below and in contact with said insulating layer.
Claim 2
Dependent Claim
236 words
A semiconductor integrated circuit comprising: a semiconductor substrate of a first conductivity type of a given impurity concentration; an active semiconductor element formed in said substrate; a protective resistor region of a second conductivity type opposite to said first conductivity type formed in the surface of the substrate, said protective resistor region being electrically connected to said active element; an input contact portion in said resistor region for connecting an input signal to said resistor region; and protective means including a metal oxide semiconductor field effect transistor formed to substantially surround said resistor region and electrically connected to said resistor region for being rendered conductive only by excessive voltage surges applied to said input contact portion of said resistor region and for absorbing such excess voltage surges and thereby protecting said active element; wherein said metal oxide semiconductor field effect transistor is comprised of said resistor region; a second conductivity type region in the semiconductor substrate substantially surrounding at least the input contact portion of said resistor region; an insulating layer formed adjacent to and insulating said second conductivity type region from said resistor region; a conducting layer formed at least in part on the insulating layer and extending over at least a part of said resistor region; and a channel stopper region of said first conductivity type having a higher impurity concentration than said substrate and located below and in contact with said insulating layer.
Claim 3
Dependent Claim
26 words
The semiconductor integrated circuit of claim 1 further including an additional insulating layer abutting the periphery of said second conductivity type region of said protective means.
Claim 4
Dependent Claim
41 words
The semiconductor integrated circuit of claim 2 further including a second channel stopper region of said first conductivity type having a higher impurity concentration than said substrate, said second semiconductor region located below and in contact with said additional insulating layer.
Claim 5
Dependent Claim
168 words
A semiconductor integrated circuit device comprising: a semiconductor substrate of first conductivity type; an insulated gate field effect transistor (IGFET) formed in the semiconductor substrate and having a gate region; a protective resistor region of second conductivity type opposed to the first conductivity type formed in a surface of the semiconductor substrate, said protective resistor region being connected to the gate region of the IGFET; an input terminal; an input contact portion of the resistor region for connecting the input terminal to the resistor region; another second conductivity type region in the semiconductor substrate adjacent said resistor region and substantially surrounding at least the input portion; a thin insulating film bridging the resistor region and the another second conductivity region; and a conductive layer formed on the thin insulating film and in contact with the another second conductivity type region, wherein there is a surface breakdown between the resistor region and the another second conductivity type region when an excessively high voltage is applied to the input terminal.
Claim 6
Dependent Claim
168 words
A semiconductor integrated circuit device comprising: a semiconductor substrate of first conductivity type; an insulated gate field effect transistor (IGFET) formed in the semiconductor substrate and having a gate region; a protective resistor region of second conductivity type opposed to the first conductivity type formed in a surface of the semiconductor substrate, said protective resistor region being connected to the gate region of the IGFET; an input terminal; an input contact portion of the resistor region for connecting the input terminal to the resistor region; another second conductivity type region in the semiconductor substrate adjacent said resistor region and substantially surrounding at least the input portion; a thin insulating film bridging the resistor region and the another second conductivity region; and a conductive layer formed on the thin insulating film and in contact with the another second conductivity type region, wherein there is a surface breakdown between the resistor region and the another second conductivity type region when an excessively high voltage is applied to the input terminal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-04-01 | 1988-10-01 | 1989-04-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-04-01 | 1992-10-01 | 1993-04-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-04-01 | 1996-10-01 | 1997-04-02 | $7700.00 | Window Closed / Lapsed |