Insulated gate field effect transistor

Claim 2

An insulated gate field effect transistor comprising a semiconductor substrate of one conductivity type, a source region and a drain region of the opposite conductivity type provided along one principal surface of said semiconductor substrate, a channel region between said source region and said drain region, a gate electrode provided on said channel region via a gate insulating film, and an impurity region of said one conductivity type having a higher impurity concentration than said semiconductor substrate, said impurity region being provided in contact with substantially the entire bottom of said source region excluding the side wall of said source region facing said channel region, said impurity region being led out to said one principal surface through a portion of said substrate other than said channel region and being ohmically connected to a source electrode jointly with said source region, said impurity region having an impurity concentration of 1×10 18 cm -3 or higher, said semiconductor substrate having a bottom surface opposite to said one principal surface, said semiconductor substrate between said drain region and said bottom surface having an impurity concentration less than 1×10 18 cm -3 .

Claim 3

An insulated gate field effect transistor as claimed in claim 1, in which said semiconductor substrate includes a semiconductor base body of said one conductivity type having a lower impurity concentration than said impurity region and a semiconductor layer of said one conductivity type formed on said semiconductor base body and having a lower impurity concentration than said impurity region.

Claim 4

An insulated gate field effect transistor comprising a semiconductor substrate of one conductivity type, source and drain regions of the opposite conductivity type formed in one principal surface of said semiconductor substrate, an offset gate region of the opposite conductivity type having a lower impurity concentration than that of said drain region and being formed along said major surface and abutted against said drain region and extending towards said source region, a channel portion between said source region and said offset gate region, a gate insulating film on said channel portion, a gate electrode on said gate insulating film, and a buried layer of said one conductivity type and having higher impurity concentration than that of said semiconductor substrate, said buried layer being formed under substantially the entire bottom of said source region and being led out to said principal surface through a portion of said substrate other than said channel portion, said buried layer having an impurity concentration of 1×10 18 cm -3 or higher, said semiconductor substrate having a bottom surface opposite to said one principal surface, and said buried layer not extending between said drain region and said bottom surface of said semiconductor substrate.

Claim 5

An insulated gate field effect transistor comprising a semiconductor substrate of one conductivity type, source and drain regions of the opposite conductivity type formed in one principal surface of said semiconductor substrate, an offset gate region of the opposite conductivity type having a lower impurity concentration than that of said drain region and being formed along said major surface and abutted against said drain region and extending towards said source region, a channel portion between said source region and said offset gate region, a gate insulating film on said channel portion, a gate electrode on said gate insulating film, and a buried layer of said one conductivity type and having higher impurity concentration than that of said semiconductor substrate, said buried layer being formed under substantially the entire bottom of said source region and being led out to said principal surface through a portion of said substrate other than said channel portion, said buried layer having an impurity concentration of 1×10 18 cm -3 or higher, said semiconductor substrate having a bottom surface opposite to said one principal surface, and said buried layer not extending between said drain region and said bottom surface of said semiconductor substrate.

Claim 6

An insulated gate field effect transistor as claimed in claim 3, in which said buried layer extends up to a location right under the end of said offset gate region.

Claim 7

An insulated gate field effect transistor comprising a semiconductor substrate of one conductivity type, a drain region of the opposite conductivity type provided along one principal surface of said semiconductor substrate, an offset gate region of said opposite conductivity type having a lower impurity concentration than said drain region and a shallower depth than said drain region, said offset gate region extending from said drain region and disposed so as to surround said drain region, a channel region formed in a ring shape surrounding said offset region, a ring-shaped gate electrode provided on said channel region via a gate insulating film, a source region of the opposite conductivity type formed in a ring shape surrounding said channel region with its inner circumference adjoining the channel region, an impurity region of said one conductivity type having a higher impurity concentration than said semiconductor substrate, said impurity region contacting with substantially the entire bottom surface of said source region, said impurity region adjoining the outer circumference of said source region and being led out to said one principal surface of the semiconductor substrate, and a source electrode connected in common to said source region and said impurity region, said impurity region having an impurity concentration of 1×10 18 cm -3 or higher, said semiconductor substrate having a bottom surface opposite to said one principal surface, and said impurity region not extending between said drain region and said bottom surface of said semiconductor substrate.

Claim 8

An insulated gate field effect transistor comprising a semiconductor substrate of one conductivity type, a drain region of the opposite conductivity type provided along one principal surface of said semiconductor substrate, an offset gate region of said opposite conductivity type having a lower impurity concentration than said drain region and a shallower depth than said drain region, said offset gate region extending from said drain region and disposed so as to surround said drain region, a channel region formed in a ring shape surrounding said offset region, a ring-shaped gate electrode provided on said channel region via a gate insulating film, a source region of the opposite conductivity type formed in a ring shape surrounding said channel region with its inner circumference adjoining the channel region, an impurity region of said one conductivity type having a higher impurity concentration than said semiconductor substrate, said impurity region contacting with substantially the entire bottom surface of said source region, said impurity region adjoining the outer circumference of said source region and being led out to said one principal surface of the semiconductor substrate, and a source electrode connected in common to said source region and said impurity region, said impurity region having an impurity concentration of 1×10 18 cm -3 or higher, said semiconductor substrate having a bottom surface opposite to said one principal surface, and said impurity region not extending between said drain region and said bottom surface of said semiconductor substrate.

Claim 9

An insulated gate field effect transistor as claimed in claim 2, wherein said semiconductor layer is an epitaxial layer of relatively small thickness as compared to said semiconductor base body, said semiconductor layer and said semiconductor base body having substantially equivalent impurity concentrations.

Claim 10

An insulated gate field effect transistor as claimed in claim 3, wherein said source region and said buried layer are commonly connected, and wherein said buried layer substantially surrounds the outer peripheral surface of said source region.

Claim 11

An insulated gate field effect transistor as claimed in claim 7, wherein said buried layer abuts said source region along the bottom and outer peripheral surfaces thereof.

Claim 12

An insulated gate field effect transistor as claimed in claim 7, wherein said source region and said buried layer are separated by a low impurity concentration layer.