Insulated gate type semiconductor device

Claim 2

An insulated gate type transistor formed in a semiconductor chip, comprising: a heavily-doped source semiconductor region of a first conductivity type, for supplying charge carriers; a heavily-doped drain semiconductor region of said first conductivity type, for receiving the carriers supplied from said source; a channel semiconductor region formed between said source and drain regions, having a second conductivity type opposite to said first conductivity type; an insulated gate structure including an insulating film formed on said channel semiconductor region and a conductive gate electrode formed on said insulating film; said channel region having such dimensions and a resistivity that the potential profile from said source region to said drain region for the carriers supplied from said source has a potential barrier which can be controlled by potentials of said gate structure and of said drain region, and means provided in the neighborhood of said source region for increasing the ratio of the amount of carriers reaching said drain region to the total amount of carriers supplied from said source region.

Claim 3

An insulated gate type transistor according to claim 1, wherein: said source and drain regions are formed in said semiconductor chip adjacent to a principal surface thereof, and said means comprises said heavily-doped source semiconductor region having a shallower depth than that of said heavily-doped drain region.

Claim 4

An insulated gate type transistor according to claim 2, further comprising: a subsidiary drain semiconductor region of said first conductivity type and of high resistivity, formed in said semiconductor chip, disposed around said drain region and at least between said channel semiconductor region and drain region.

Claim 5

An insulated gate type transistor according to claim 1, wherein: said means comprises a suppressing semiconductor region of said second conductivity type having a resistivity lower than that of said channel region formed adjacent to a portion of said source region so as to eliminate injection of carriers therefrom.

Claim 6

An insulated gate type transistor according to claim 4, wherein: said source region and said drain region are formed in said semiconductor chip adjacent to a principal surface thereof, and said suppressing semiconductor region is located adjacent to at least a bottom portion of said source region in said semiconductor chip.

Claim 7

An insulated gate type transistor according to claim 5, wherein: said suppressing semiconductor region has a surface extending from said bottom portion of said source region toward said drain region and defining a boundary of said channel semiconductor region.

Claim 8

An insulated gate type transistor according to claim 6, wherein: said channel semiconductor region is formed between said principal surface and said suppressing semiconductor region, and the transistor further comprises: a subsidiary drain semiconductor region of said first conductivity type having a higher resistivity than that of said drain region and formed around said drain region and also adjacent to said channel and the suppressing semiconductor regions.

Claim 9

An insulated gate type transistor according to claim 7, wherein: said drain region has a depth greater than that of said source region.

Claim 10

An insulated gate type transistor according to claim 8, wherein: said drain region has a shape approaching said source region as this shape goes deeper toward the bottom of substrate.

Claim 11

An insulated gate type integrated semiconductor device formed in a semiconductor chip and including at least one insulated gate transistor, said insulated gate transistor comprising: a heavily-doped source semiconductor region of a first conductivity type for supplying charge carriers; a heavily-doped drain semiconductor region of said first conductivity type for receiving the carriers supplied from said source; a channel semiconductor region formed between said source and drain regions and having a second conductivity type opposite to said first conductivity type; an insulated gate structure including an insulating film formed on said channel semiconductor region and a conductive gate electrode formed on said insulating film; said channel region having such dimensions and a resistivity that the potential profile from said source region to said drain region for the carriers supplied from said source has a potential barrier which can be controlled by potentials of said gate structure and of said drain region; and means provided in the neighborhood of said source region for increasing the ratio of the amount of carriers supplied from said source region, controlled by the potential of said gate structure, and reaching said drain region, to the total amount of carriers injected from said source region.

Claim 12

An insulated gate type integrated semiconductor device formed in a semiconductor chip and including at least one insulated gate transistor, said insulated gate transistor comprising: a heavily-doped source semiconductor region of a first conductivity type for supplying charge carriers; a heavily-doped drain semiconductor region of said first conductivity type for receiving the carriers supplied from said source; a channel semiconductor region formed between said source and drain regions and having a second conductivity type opposite to said first conductivity type; an insulated gate structure including an insulating film formed on said channel semiconductor region and a conductive gate electrode formed on said insulating film; said channel region having such dimensions and a resistivity that the potential profile from said source region to said drain region for the carriers supplied from said source has a potential barrier which can be controlled by potentials of said gate structure and of said drain region; and means provided in the neighborhood of said source region for increasing the ratio of the amount of carriers supplied from said source region, controlled by the potential of said gate structure, and reaching said drain region, to the total amount of carriers injected from said source region.

Claim 13

An insulated gate type integrated semiconductor device according to claim 10, wherein: said source and drain regions are formed in said semiconductor chip adjacent to a principal surface thereof, and said means comprises said heavily-doped source semiconductor region having a shallower depth from said surface than that of said heavily-doped drain region.

Claim 14

An insulated gate type integrated semiconductor device according to claim 10, wherein: said means comprises a suppressing semiconductor region of said second conductivity type having a resistivity lower than that of said channel region formed adjacent to a portion of said source region so as to eliminate injection of carriers therefrom.

Claim 15

An insulated gate type transistor formed in a semiconductor chip, comprising: a heavily-doped source semiconductor region of a first conductivity type, for supplying charge carriers; a heavily-doped drain semiconductor region of said first conductivity type, for receiving the carriers supplied from said source; a channel semiconductor region formed between said source and drain regions, having a second conductivity type opposite to said first conductivity type; an insulated gate structure including an insulating film formed on said channel semiconductor region and a conductive gate electrode formed on said insulating film; means for completely depleting said channel region and for generating a potential barrier being responsive to the respective potentials of both said gate and said drain; and means for orienting carriers supplied from said source to said drain through said potential barrier.

Claim 16

An insulated gate type transistor formed in a semiconductor chip, comprising: a heavily-doped source semiconductor region of a first conductivity type, for supplying charge carriers; a heavily-doped drain semiconductor region of said first conductivity type, for receiving the carriers supplied from said source; a channel semiconductor region formed between said source and drain regions, having a second conductivity type opposite to said first conductivity type; an insulated gate structure including an insulating film formed on said channel semiconductor region and a conductive gate electrode formed on said insulating film; means for completely depleting said channel region and for generating a potential barrier being responsive to the respective potentials of both said gate and said drain; and means for orienting carriers supplied from said source to said drain through said potential barrier.

Claim 17

The transistor of claim 1 wherein: said source and drain regions are each disposed adjacent to a first principal surface of said chip, and said means for directing comprises said source and drain regions, where said drain region extends to a greater depth from said first principle surface than said drain region.

Claim 18

The transistor of claims 13 or 14 wherein: said means for directing comprises a carrier suppression semiconductor region of said second conductivity type and of a higher impurity concentration than that of said channel region, said carrier suppression region being disposed adjacently underlying said source region.

Claim 19

The transistor of claim 15 wherein said suppression region includes a portion extending laterally beyond said source towards said drain.