Diffusion self aligned mosfet with pinch off isolation

Abstract

Abstract AN INSULATED GATE FIELD-EFFECT TRANSISTOR COMPRISES A SEMICONDUCTOR SUBSTRATE HAVING A FIRST AND SECOND REGION OF OPPOSITE CONDUCTIVITY TYPE FROM THE SUBSTRATE AND HAVING AN IMPURITY CONCENTRATION GREATER THAN THE SUBSTRATE SO AS TO DEVELOP DEPLETION LAYERS THEREBETWEEN. A SOURCE REGION AND A DRAIN OF THE SAME CONDUCTIVITY TYPE AS THE SUBSTRATE ARE FORMED IN THE FIRST REGION AND THE SECOND REGION RESPECTIVELY. THE DEPLETION LAYERS MEET TO ELECTRICALLY ISOLATE A CHANNEL BETWEEN THE DRAIN AND SOURCE REGIONS FROM THE REST OF THE SUBSTRATE. AN INSULATING LAYER OVERLIES THE CHANNEL, A GATE ELECTRODE IS DISPOSED ON THE INSULATING LAYER, AND METALLIC SOURCE AND DRAIN ELECTRODES MAKE OHMIC CONTACT WITH THE SOURCE AND DRAIN RESPECTIVELY. A PLURALITY OF INSULATED GATE-FIELD EFFECT TRANSISTORS ARE FABRICATED IN AN INTEGRATED CIRCIT TO FORM COMPLEMENTARY PAIRS.

Inventors

• 👤 Y Hayashi
• 👤 Y Tarui

Bibliographic Details