Semiconductor storage device

Claim 2

A semiconductor storage device comprising: a semiconductor substrate; a plurality of separate storage regions formed in the semiconductor substrate the dimensions of each of which being dependent upon the analog value to be stored therein whereby analog sampling values are stored in said storage device.

Claim 3

A semiconductor storage device which comprises: a storage section which is adapted to store analog sampling values substantially in the form of resistance values said storage section being formed in a semiconductor substrate and having a plurality of separate storage regions the dimensions of each of which being dependent upon the analog value to be stored therein; and a read-out control circuit operatively associated with said storage section for introducing readout signals thereto in response to read-out control instructions from said read-out control circuit, whereby analog information is obtained from the read-out signals.

Claim 4

A semiconductor storage device which comprises: a storage section which is adapted to store analog sampling values substantially in the form of resistance values said storage section being formed in a semiconductor substrate and having a plurality of separate storage regions the dimensions of each of which being dependent upon the analog value to be stored therein; and a read-out control circuit operatively associated with said storage section for introducing readout signals thereto in response to read-out control instructions from said read-out control circuit, whereby analog information is obtained from the read-out signals.

Claim 5

A semiconductor storage device adapted to store analog sampling values comprising: a plurality of belt-like diffusion resistance layers formed on a semiconductor substrate said layers being of the same width but of different effective lengths, which lengths are proportional to the resistance of the layers so that the analog sampling values can be stored therein and represented by the respective resistance values of the layers; an insulating layer laid on said diffusion resistance layers and having ''''contact-cut'''' areas for providing contact therethrough to said layers and disposed at predetermined intervals lengthwise of each diffusion resistance layer; and an electrically conductive layer having a side line which has a predetermined shape and traverses all the diffusion resistance layes so as to cover at least one of said contact-cut portions, whereby in the region which is not covered with the electrically conductive layer the effective lengths of said diffusion resistance layers are the distances between the point which the trace of said side line makes on the diffusion resistance layers and the ends of the diffusion resistance layer.

Claim 6

A semiconductor storage device adapted to store analog sampling values comprising: a plurality of belt-like diffusion resistance layers formed on a semiconductor substrate said layers being of the same width but of different effective lengths, which lengths are proportional to the resistance of the layers so that the analog sampling values can be stored therein and represented by the respective resistance values of the layers; an insulating layer laid on said diffusion resistance layers and having ''''contact-cut'''' areas for providing contact therethrough to said layers and disposed at predetermined intervals lengthwise of each diffusion resistance layer; and an electrically conductive layer having a side line which has a predetermined shape and traverses all the diffusion resistance layes so as to cover at least one of said contact-cut portions, whereby in the region which is not covered with the electrically conductive layer the effective lengths of said diffusion resistance layers are the distances between the point which the trace of said side line makes on the diffusion resistance layers and the ends of the diffusion resistance layer.

Claim 7

A semiconductor storage device comprising: a diffusion resistance layer having a plurality of connecting portions and having a voltage applied across two ends of the layer; a plurality of transistors each of which has a gate electrode and a source and drain junction, each of said sources being connected to respective ones of said connecting portions; a plurality of diffusion layers to one end of each of said read-out signals are applied; and a plurality of electrically conductive belt-like layers which cross the diffusion layers to form a grid-like array each being connected at one thereof to the gate of a respective one of said transistors; an insulating layer interposed between the diffusion layers and the electrically conductive layer, said diffusion layers and said electrically conductive layers being selectively connected together through a plurality of ''''contact-cut'''' portions each corresponding to an analog sampling value to be stored, provided in said insulating layer on each of the diffusion layers at predetermined intervals lengthwise thereof, the read-out signals being applied to respective gates of the transistors through respective selected diffusion and electrically conductive layers which selected layers arE connected together by said ''''contact-cut'''' portions, whereby said transistors become conductive and voltages appearing at each one of said connecting portions are read out through the sources of respective ones of said transistors.

Claim 8

A semiconductor storage device comprising: a diffusion resistance layer having a plurality of connecting portions and having a voltage applied across two ends of the layer; a plurality of transistors each of which has a gate electrode and a source and drain junction, each of said sources being connected to respective ones of said connecting portions; a plurality of diffusion layers to one end of each of said read-out signals are applied; and a plurality of electrically conductive belt-like layers which cross the diffusion layers to form a grid-like array each being connected at one thereof to the gate of a respective one of said transistors; an insulating layer interposed between the diffusion layers and the electrically conductive layer, said diffusion layers and said electrically conductive layers being selectively connected together through a plurality of ''''contact-cut'''' portions each corresponding to an analog sampling value to be stored, provided in said insulating layer on each of the diffusion layers at predetermined intervals lengthwise thereof, the read-out signals being applied to respective gates of the transistors through respective selected diffusion and electrically conductive layers which selected layers arE connected together by said ''''contact-cut'''' portions, whereby said transistors become conductive and voltages appearing at each one of said connecting portions are read out through the sources of respective ones of said transistors.

Claim 9

A semiconductor storage device comprising: a common diffusion resistance layer having a plurality of connecting portions; a plurality of transistors each having a source, drain and gate electrode with each of said sources being connected to respective ones of said connecting portions; a plurality of belt-like diffusion layers to one end of each of which read-out signals are applied; and a plurality of electrically conductive belt-like layers which cross the diffusion layers to form a grid-like array each being connected at one end thereof to the gate of a respective one of said transistors; an insulating layer interposed between said diffusion layers and said electrically conductive layers and having ''''contact-cut'''' portions for selectively connecting together said diffusion and electrically conductive layers, the read-out signals being applied to respective gates of said transistors through respective selected diffusion and electrically conductive layers which selected layers are connected together through said ''''contact-cut'''' portions whereby said transistors become conductive and voltages appearing at the connecting portions are read out through respective sources of said transistors; and in which said common diffusion resistance layer is formed as a belt, having said plurality of connecting portions and a voltage of a predetermined value is applied between one end of said belt-like diffusion resistance layer and an elongated portion which is positioned on the side opposite to that side having said connecting portions and in direction lengthwise of said diffusion resistance layer.

Claim 10

A semiconductor storage device comprising: a common diffusion resistance layer having a plurality of connecting portions; a plurality of transistors each having a source, drain and gate electrode with each of said sources being connected to respective ones of said connecting portions; a plurality of belt-like diffusion layers to one end of each of which read-out signals are applied; and a plurality of electrically conductive belt-like layers which cross the diffusion layers to form a grid-like array each being connected at one end thereof to the gate of a respective one of said transistors; an insulating layer interposed between said diffusion layers and said electrically conductive layers and having ''''contact-cut'''' portions for selectively connecting together said diffusion and electrically conductive layers, the read-out signals being applied to respective gates of said transistors through respective selected diffusion and electrically conductive layers which selected layers are connected together through said ''''contact-cut'''' portions whereby said transistors become conductive and voltages appearing at the connecting portions are read out through respective sources of said transistors; and in which said common diffusion resistance layer is formed as a belt, having said plurality of connecting portions and a voltage of a predetermined value is applied between one end of said belt-like diffusion resistance layer and an elongated portion which is positioned on the side opposite to that side having said connecting portions and in direction lengthwise of said diffusion resistance layer.