Semiconductor integrated circuit device including bonding pads and fabricating method thereof

Claim 2

A semiconductor integrated circuit device comprising: a semiconductor substrate; a plurality of I/O cells formed on said semiconductor substrate, each of said I/O cells including predetermined circuit elements capable of being interconnected to provide at least one of the circuit functions of an input circuit, an output circuit and an input/output circuit; a plurality of bonding pads formed on said semiconductor substrate corresponding to respective I/O cells, with each I/O cell having at least two independent bonding pads in correspondence therewith, the number of bonding pads exceeding the number of I/O cells, said at least two bonding pads being adjacent to each other; and a wiring pattern for providing each of said I/O cells with at least two selected circuits of said input, output and input/output circuits, said wiring pattern including an interconnection for electrically connecting each of said I/O cells with at least two of said corresponding bonding pads to extract said two selected circuits from each I/O cell.

Claim 3

A semiconductor integrated circuit device according to claim 1, wherein one of the two bonding pads, which are provided for each of said I/O cells, is adapted to supply the input circuit of the I/O cell with a signal whereas the other of said bonding pads is adapted to derive a signal from the output circuit of the I/O cell.

Claim 4

A semiconductor integrated circuit device according to claim 1 or 2, wherein each of said bonding pads is composed of a lower conductor film and an upper conductor film overlaid on and in contact with the former.

Claim 7

A fabricating method according to claim 4, wherein said at least two bonding pads are formed adjacent to said respective I/O cell.

Claim 8

A semiconductor integrated circuit device according to claim 1, wherein said at least two bonding pads in correspondence with said respective I/O cells are positioned adjacent to said respective I/O cells.

Claim 9

A semiconductor integrated circuit device comprising: a semiconductor substrate; a plurality of I/O cells formed on said semiconductor substrate, each of said I/O cells including predetermined circuit elements capable of being interconnected to provide at least one of the circuit functions of an input circuit, an output circuit and an input/output circuit; a plurality of bonding pads formed on said semiconductor substrate corresponding to I/O cells, each of the bonding pads corresponding to a respective I/O cell being located adjacent said respective I/O cell, at least one of the I/O cells having at least two bonding pads corresponding thereto, the number of bonding pads exceeding the number of I/O cells; and a wiring pattern for providing each of said I/O cells with selected circuits providing said at least one of the circuit functions, said wiring pattern including an interconnection for electrically connecting each of said I/O cells with said corresponding bonding pads to extract said selected circuits providing said at least one of the circuit functions from each I/O cell.

Claim 10

A semiconductor integrated circuit device comprising: a semiconductor substrate; a plurality of I/O cells formed on said semiconductor substrate, each of said I/O cells including predetermined circuit elements capable of being interconnected to provide at least one of the circuit functions of an input circuit, an output circuit and an input/output circuit; a plurality of bonding pads formed on said semiconductor substrate corresponding to I/O cells, each of the bonding pads corresponding to a respective I/O cell being located adjacent said respective I/O cell, at least one of the I/O cells having at least two bonding pads corresponding thereto, the number of bonding pads exceeding the number of I/O cells; and a wiring pattern for providing each of said I/O cells with selected circuits providing said at least one of the circuit functions, said wiring pattern including an interconnection for electrically connecting each of said I/O cells with said corresponding bonding pads to extract said selected circuits providing said at least one of the circuit functions from each I/O cell.

Claim 11

A semiconductor integrated circuit device according to claim 7, wherein a single bonding pad corresponds to a respective I/O cell, said single bonding pad being adjacent said respective I/O cell.

Claim 14

A fabricating method according to claim 9, wherein said interconnecting at least some of the circuit elements and said forming bonding pads are performed simultaneously.

Claim 17

A fabricating method according to claim 11, further including interconnecting at least some of the circuit elements of each of said I/O cells in a pattern so as to provide said at least one predetermined circuit function.

Claim 18

A fabricating method according to claim 12, wherein said plurality of I/O cells are located on a first area of the semiconductor substrate, the substrate also including thereon a plurality of rows of unit cells, for providing a logic circuit, said plurality of rows of unit cells being formed on a second area of said substrate different from the first area.

Claim 19

A fabricating method according to claim 13, wherein said first area extends around the periphery of the second area.

Claim 20

A fabricating method according to claim 11, wherein at least two bonding pads are formed to correspond to each I/O cell, said at least two bonding pads being adjacent each other.

Claim 21

A fabricating method according to claim 15, wherein at least one of said I/O cells is provided with two circuits to provide said at least one predetermined circuit function, the method further including connecting each of said at least one of the I/O cells to two bonding pads formed to correspond thereto.

Claim 22

A fabricating method according to claim 11, wherein said bonding pads are formed by forming a lower conductor film on the semiconductor substrate and an upper conductor film overlaid on and in contact with the lower conductor film.

Claim 23

A fabricating method according to claim 8, 9 or 12, further including interconnecting bonding pads to the corresponding I/O cells.

Claim 24

A fabricating method according to claim 18, wherein said interconnecting bonding pads to the corresponding I/O cells is performed simultaneously with said interconnecting at least some of the circuit elements of each of said I/O cells.

Claim 25

A fabricating method according to claim 18, wherein said forming bonding pads, said interconnecting bonding pads to the corresponding I/O cells, and said interconnecting at least some of the circuit elements of each of said I/O cells are performed simultaneously.

Claim 26

Product formed by the process of claim 11.

Claim 27

Product formed by the process of claim 13.

Claim 28

Product formed by the process of claim 15.

Claim 29

Product formed by the process of claim 18.