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JPS5619639A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Hitachi Ltd
•
Filing: 1979-07-27
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Granted: —
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Expires: 1999-07-27
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Abstract

Abstract PURPOSE:To flatten the peripheral edge of a pad and prevent improper bonding of wires to the semiconductor device by increasing the size A of an opening for a lower insulator film on a substrate larger than the size B of an opening for an insulating film of an upper layer and the size A of the opening of the lower layer larger than the that of the electrode pad. CONSTITUTION:An SiO2 film 2 and PSG film 3 are formed on the Si substrate 1. The first aluminum film 4 becoming a wiring terminal forms a square having one side D, the second aluminum film 6 forming the bonding surface has one side A, a square opening having one side A is perforated at the organic resin film 5 of the lower layer, and a square opening having one side B is formed at the organic resin film 7 of the upper layer. Their sizes may satisfy the relationship of A>C>B>D, where the horizontally moving directions of the capillary of a bonder are X, Y and Y'. This configuration remarkably reduces the relative height of the upper surface of the resin on the peripheral edge of the bonding pad and the aluminum main surface so as to largely reduce the probability of failing the bonding therebetween.

Inventors

  • 👤 Akihiro Tomosawa
  • 👤 Masami Kiyono
  • 👤 Isao Sakamoto
  • 👤 Jiro Sakaguchi
  • 👤 Tokio Kato
  • 👤 Satoshi Meguro

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-03 13:06
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/90; H10W72/921; H10W72/923; H10W72/951; H10W72/952; H10W72/981; H10W72/983

Claims Analysis

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References Cited (Backward Citations)

JPS5317165U Cited

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