US4388755A
Expired / Lapsed
US
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Structure for and method of manufacturing a semiconductor device by the master slice method
Assignee: Fujitsu Ltd
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Filing: 1980-11-17
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Granted: 1983-06-21
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Expires: 2000-11-17
Abstract
Abstract A structure and method for manufacturing semiconductor devices by the master slice method, in which various kinds of semiconductor devices are manufactured through utilization of a common master pattern and a plurality of different kinds of selective wiring patterns. A number of bipolar transistors each having plural emitter regions, is formed in a predetermined region, or portion, of a semiconductor substrate by employing a common master pattern, and the plural emitter regions of the respective bipolar transistors are selectively connected by the associated wiring patterns of each thereof to form corresponding bipolar transistors of different, predetermined D.C. characteristics. When manufacturing many different kinds of semiconductor devices by the master slice method, the area which would be wasted on the semiconductor substrate by prior art techniques is greatly reduced, thus providing for enhanced area efficiency.
Inventors
- 👤 Hiromu Enomoto
- 👤 Yasushi Yasuda
- 👤 Yoshiharu Mitono
- 👤 Taketo Imaizumi
- 👤 Hitoshi Ohmichi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 00:25
CPC Classifications
H; H10; H10W; H10W72/00; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/133; H10D62/135; H10D84/00; H10D84/90; H10D84/901
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
158 words
A master slice method for forming semiconductor devices of selectively different kinds, each such device comprising a predetermined plurality of bipolar transistors respectively having common, predetermined DC characteristics and substantially similar, desired values of emitter current densities, comprising: providing a semiconductor substrate of predetermined area for each such semiconductor device, employing a common master pattern to form said predetermined plurality of bipolar transistors in a predetermined portion of said area of said semiconductor substrate provided for each said semiconductor device, including forming for each said bipolar transistor in accordance with said common master pattern, a collector region, a base region, and a predetermined plurality of emitter regions formed in said base region, and the DC characteristics of a given such semiconductor device being determined in accordance with the number of emitter regions, out of said predetermined plurality thereof, selectively connected together to form, collectively, the active emitter region of each such bipolar transistor of each said semiconductor device.
Claim 2
Dependent Claim
158 words
A master slice method for forming semiconductor devices of selectively different kinds, each such device comprising a predetermined plurality of bipolar transistors respectively having common, predetermined DC characteristics and substantially similar, desired values of emitter current densities, comprising: providing a semiconductor substrate of predetermined area for each such semiconductor device, employing a common master pattern to form said predetermined plurality of bipolar transistors in a predetermined portion of said area of said semiconductor substrate provided for each said semiconductor device, including forming for each said bipolar transistor in accordance with said common master pattern, a collector region, a base region, and a predetermined plurality of emitter regions formed in said base region, and the DC characteristics of a given such semiconductor device being determined in accordance with the number of emitter regions, out of said predetermined plurality thereof, selectively connected together to form, collectively, the active emitter region of each such bipolar transistor of each said semiconductor device.
Claim 3
Dependent Claim
77 words
A master slice method as recited in claim 1, further comprising: forming a wiring pattern for each said semiconductor device for selectively connecting together said number of emitter regions, out of said plurality thereof, of each said bipolar transistor of said semiconductor device in accordance with the predetermined DC characteristics thereof for maintaining said desired value of emitter current density for a required emitter current level of each said respective bipolar transistor of each said semiconductor device.
Claim 4
Dependent Claim
49 words
A master slice method as recited in claims 1 or 2, further comprising defining, in accordance with said master pattern, a contact window to permit electrical connection to each of said collector region and said base region, and to each of said emitter regions of each said bipolar transistor.
Claim 5
Dependent Claim
37 words
A master slice method as recited in claims 1 or 2 further comprising forming, in accordance with said master pattern, emitter regions of substantially the same size for each said bipolar transistor of each said semiconductor device.
Claim 6
Dependent Claim
34 words
A method as recited in claim 1 or 2 further comprising: selectively electrically connecting together said desired emitter regions of each said bipolar transistor in a common emitter configuration for the said bipolar transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-06-20 | 1986-12-20 | 1987-06-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-06-20 | 1990-12-20 | 1991-06-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-06-20 | 1994-12-20 | 1995-06-21 | $7700.00 | Window Closed / Lapsed |