Patent US2363545A successfully refreshed from Google Patents.
Patent US7348237B2 successfully refreshed from Google Patents.
US7348237B2
Expired / Lapsed
US
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NOR flash memory cell with high storage density
Assignee: Micron Technology Inc
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Filing: 2004-12-06
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Granted: 2008-03-25
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Expires: 2024-12-06
Abstract
Abstract Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate. The floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric. A sourceline is formed in a trench adjacent to the vertical floating gate transistor and coupled to the first source/drain region. A transmission line coupled to the second source/drain region. And, a wordline is coupled to the control gate perpendicular to the sourceline.
Inventors
- 👤 Leonard Forbes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:25
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; H; H10; H10B; H10B41/00; H10B41/20; H10B41/23; H10B41/27; H10B41/30; H10B69/00; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; H10D30/686; G11C2216/00; G11C2216/12; G11C2216/28
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
269 words
A method for forming a NOR flash memory array, comprising: forming a number of vertical pillars formed in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein forming the number of vertical pillars includes forming the number of vertical pillars to serve as floating gate transistors including a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel by a first gate insulator in the trenches along rows of pillars, and a control gate separated from the floating gate by a second gate insulator, wherein along columns of the pillars adjacent pillars include a floating gate transistor which operates as a programmed cell on one side of a trench and a floating gate transistor which operates as a reference cell having a programmed conductivity state on the opposite side of the trench; forming a number of bit lines coupled to the second source/drain region of each transistor along rows of the memory array; forming a number of word lines coupled to the control gate of each floating gate transistor along columns of the memory array; forming a number of sourcelines in a bottom of the trenches between rows of the pillars and coupled to the first source/drain regions of each floating gate transistor along rows of pillars, wherein a portion of the sourcelines undercut the pillars to form the first source/drain regions, wherein along columns of the pillars the first source/drain region of each transistor in column adjacent pillars couples to the sourceline in a shared trench.
Claim 2
Independent Claim
269 words
A method for forming a NOR flash memory array, comprising: forming a number of vertical pillars formed in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein forming the number of vertical pillars includes forming the number of vertical pillars to serve as floating gate transistors including a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel by a first gate insulator in the trenches along rows of pillars, and a control gate separated from the floating gate by a second gate insulator, wherein along columns of the pillars adjacent pillars include a floating gate transistor which operates as a programmed cell on one side of a trench and a floating gate transistor which operates as a reference cell having a programmed conductivity state on the opposite side of the trench; forming a number of bit lines coupled to the second source/drain region of each transistor along rows of the memory array; forming a number of word lines coupled to the control gate of each floating gate transistor along columns of the memory array; forming a number of sourcelines in a bottom of the trenches between rows of the pillars and coupled to the first source/drain regions of each floating gate transistor along rows of pillars, wherein a portion of the sourcelines undercut the pillars to form the first source/drain regions, wherein along columns of the pillars the first source/drain region of each transistor in column adjacent pillars couples to the sourceline in a shared trench.
Claim 3
Dependent Claim
56 words
The method of claim 1 , wherein forming each floating gate includes forming each floating gate as a vertical floating gate in a trench below a top surface of each pillar, and forming a pair of floating gates in each trench on opposing sides of the trench and opposing the channel regions in column adjacent pillars.
Claim 4
Dependent Claim
65 words
The method of claim 2 , wherein the method includes forming the control gate in the trench below the top surface of the pillars and between the pair of floating gates, such that each pair of floating gates shares a single control gate, and wherein forming each floating gate includes forming a vertically oriented floating gate having a vertical length of less than 100 nanometers.
Claim 5
Dependent Claim
66 words
The method of claim 2 , wherein the method includes forming the control gates in the trench below the top surface of the pillars and between the pair of floating gates, such that each trench houses a pair of control gates each addressing a floating gate on opposing sides of the trench respectively, and wherein the pair of control gates are separated by an insulator layer.
Claim 6
Dependent Claim
38 words
The method of claim 2 , wherein the method includes forming the control gates disposed vertically above the floating gates, and forming the control gates such that each pair of floating gates shares a single control gate line.
Claim 7
Dependent Claim
22 words
The method of claim 2 , wherein the method includes forming a pair of control gates disposed vertically above the floating gates.
Claim 8
Dependent Claim
86 words
The method of claim 1 , wherein forming each floating gate includes forming each floating gate as a horizontally oriented floating gate in a trench below a top surface of each pillar, such that each trench houses a floating gate opposing the channel regions in column adjacent pillars on opposing sides of the trench, and wherein forming each horizontally oriented floating gate includes forming each horizontally oriented floating gate to have a vertical length of less than 100 nanometers opposing the channel regions of the pillars.
Claim 9
Dependent Claim
20 words
The method of claim 7 , wherein the method includes forming the control gates disposed vertically above the floating gates.
Claim 10
Dependent Claim
39 words
The method of claim 1 , wherein forming the number of sourcelines in a bottom of the trenches between rows of the pillars includes implanting a doped region in the bottom of the trenches between rows of the pillars.
Claim 11
Dependent Claim
32 words
The method of claim 1 , wherein forming the first gate insulator of each floating gate transistor includes forming the first gate insulator to have a thickness of approximately 10 nanometers (nm).
Claim 12
Dependent Claim
46 words
The method of claim 1 , wherein forming the number of vertical pillars to serve as floating gate transistors includes forming floating gate transistors which have a density equivalent to a floating gate transistor having a size of approximately 2.0 lithographic features squared (2F 2 ).
Claim 13
Independent Claim
180 words
A method for forming a NOR memory array, comprising: forming a number of NOR flash memory cells from vertical pillars extending from a substrate and separated by trenches, wherein each flash memory cell includes a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel by a first gate insulator, and a control gate separated from the floating gate by a second gate insulator; coupling a number of bit lines to the second source/drain region of each flash memory cell along rows of the memory array; coupling a number of word lines to the control gate of each flash memory cell along columns of the memory array; forming a number of sourcelines along rows in the trenches between the number of flash memory cells extending from a substrate, wherein a portion of the sourcelines undercut the pillars to form the first source/drain regions; and trapping a charge in at least one floating gate such that the flash memory cell operates at reduced drain source current.
Claim 14
Independent Claim
180 words
A method for forming a NOR memory array, comprising: forming a number of NOR flash memory cells from vertical pillars extending from a substrate and separated by trenches, wherein each flash memory cell includes a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel by a first gate insulator, and a control gate separated from the floating gate by a second gate insulator; coupling a number of bit lines to the second source/drain region of each flash memory cell along rows of the memory array; coupling a number of word lines to the control gate of each flash memory cell along columns of the memory array; forming a number of sourcelines along rows in the trenches between the number of flash memory cells extending from a substrate, wherein a portion of the sourcelines undercut the pillars to form the first source/drain regions; and trapping a charge in at least one floating gate such that the flash memory cell operates at reduced drain source current.
Claim 15
Dependent Claim
27 words
The method of claim 12 , wherein forming the floating gate includes forming a vertically oriented floating gate having a vertical length of less than 100 nanometers.
Claim 16
Dependent Claim
32 words
The method of claim 12 , wherein forming the vertical floating gate transistor includes forming a vertical floating gate transistor having a size of approximately 2.0 lithographic features squared (2F 2 ).
Claim 17
Independent Claim
195 words
A method for forming an electronic system, comprising: forming a NOR flash memory array, including: forming a number of NOR flash memory cells from vertical pillars extending from a substrate and separated by trenches, wherein each flash memory cell includes a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel by a first gate insulator, and a control gate separated from the floating gate by a second gate insulator; coupling a number of bit lines to the second source/drain region of each flash memory cell along rows of the memory array; coupling a number of word lines to the control gate of each flash memory cell along columns of the memory array; forming a number of sourcelines along rows in the trenches between the number of flash memory cells extending from a substrate, wherein a portion of the sourcelines undercut the pillars to form the first source/drain regions; trapping a charge in at least one floating gate, such that the flash memory cell operates at reduced drain source current; and coupling a processor to the NOR flash memory array.
Claim 18
Independent Claim
195 words
A method for forming an electronic system, comprising: forming a NOR flash memory array, including: forming a number of NOR flash memory cells from vertical pillars extending from a substrate and separated by trenches, wherein each flash memory cell includes a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel by a first gate insulator, and a control gate separated from the floating gate by a second gate insulator; coupling a number of bit lines to the second source/drain region of each flash memory cell along rows of the memory array; coupling a number of word lines to the control gate of each flash memory cell along columns of the memory array; forming a number of sourcelines along rows in the trenches between the number of flash memory cells extending from a substrate, wherein a portion of the sourcelines undercut the pillars to form the first source/drain regions; trapping a charge in at least one floating gate, such that the flash memory cell operates at reduced drain source current; and coupling a processor to the NOR flash memory array.
Claim 19
Dependent Claim
22 words
The method of claim 15 , wherein forming the number of sourcelines includes doping a region in the bottom of the trenches.
Claim 20
Dependent Claim
26 words
The method of claim 15 , wherein forming the floating gates includes forming a floating gate in the trenches below a top surface of the pillars.
Claim 21
Dependent Claim
27 words
The method of claim 15 , wherein forming the floating gate includes forming a vertically oriented floating gate having a vertical length of less than 100 nanometers.
References Cited (Backward Citations)
US3665423A
Cited
US3641516A
Cited
US3877054A
Cited
US3964085A
Cited
US4152627A
Cited
US4217601A
Cited
US4507673A
Cited
US4939559A
Cited
US4661833A
Cited
US5021999A
Cited
US5293560A
Cited
US4888733A
Cited
US5042011A
Cited
US5111430A
Cited
US5027171A
Cited
JPH03222367A
Cited
US5253196A
Cited
US5449941A
Cited
US5399516A
Cited
US5388069A
Cited
US5280205A
Cited
US5317535A
Cited
US5550770A
Cited
US5409859A
Cited
JPH06224431A
Cited
US5438544A
Cited
JPH06302828A
Cited
US5539279A
Cited
US6521950B1
Cited
US5493140A
Cited
US5298447A
Cited
US5467306A
Cited
US5430670A
Cited
US5424993A
Cited
US5541872A
Cited
US5541871A
Cited
US5434815A
Cited
US5508543A
Cited
US5410504A
Cited
US5485422A
Cited
US5457649A
Cited
US5572459A
Cited
US5627781A
Cited
US5600587A
Cited
US5477485A
Cited
US5891773A
Cited
JPH08255878A
Cited
US5530668A
Cited
US5530581A
Cited
US5670790A
Cited
US5714766A
Cited
US5627785A
Cited
US5768192A
Cited
US5912488A
Cited
US5916365A
Cited
US5754477A
Cited
US6166401A
Cited
US5989958A
Cited
US5959896A
Cited
US5852306A
Cited
US5801401A
Cited
US5740104A
Cited
US5856688A
Cited
US6115281A
Cited
US5936274A
Cited
US5973356A
Cited
US6238976B1
Cited
US6072209A
Cited
US6143636A
Cited
US6150687A
Cited
US5886368A
Cited
US6249020B1
Cited
US6031263A
Cited
US6552387B1
Cited
US6566699B2
Cited
US6011725A
Cited
WO1999007000A2
Cited
US6313518B1
Cited
US5828605A
Cited
US6140181A
Cited
US6351411B2
Cited
US6545314B2
Cited
US6246606B1
Cited
US6232643B1
Cited
US6252793B1
Cited
US5943262A
Cited
US6153468A
Cited
US5991225A
Cited
US6124729A
Cited
US6294813B1
Cited
US6125062A
Cited
US6141260A
Cited
US20020003252A1
Cited
US6034882A
Cited
US6185122B1
Cited
US6504755B1
Cited
US6141237A
Cited
US6212103B1
Cited
US20020027264A1
Cited
US6498362B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2011-03-25 | 2011-09-24 | 2012-03-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2015-03-25 | 2015-09-24 | 2016-03-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2019-03-25 | 2019-09-24 | 2020-03-25 | $7700.00 | Window Closed / Lapsed |