US5600587A
Expired / Lapsed
US
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Ferroelectric random-access memory
Assignee: NEC Corp
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Filing: 1996-01-29
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Granted: 1997-02-04
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Expires: 2016-01-29
Abstract
Abstract The invention provides a nonvolatile random-access memory using memory cells consisting of a ferroelectric capacitor and a switching transistor. The memory has two memory blocks each of which has memory cells arranged in rows and columns, word lines, bit lines, a plate line, sense amplifiers and reference voltage generators. The memory includes a plate line voltage control circuit which impresses supply voltage to the plate line of one memory block and ground potential to the plate line of the other memory block during a transition period preceding to read or write operation and then connects the two plate lines to thereby keep the connected plate lines at an intermediate voltage between supply voltage and ground potential. To retard fatigue of the ferroelectric material by repeated polarization in positive and negative directions, the memory can optionally be operated in a volatile mode.
Inventors
- 👤 Hiroki Koike
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:20
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/22
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
362 words
A ferroelectric random-access memory comprising first and second memory blocks each of which comprises a plurality of memory cells arranged in rows and columns, each memory cell comprising a ferroelectric capacitor, which comprises first and second electrode plates and a ferroelectric material interposed between the two electrode plates, and a field effect transistor which is coupled at the source or drain to the first electrode plate of the capacitor, each memory block further comprising a plurality of word lines each of which is arranged along a row of memory cells and is coupled to the gate of said transistor in a plurality of memory cells in the row, a plurality of bit lines each of which is arranged along a column of memory cells and is coupled to the drain or source of said transistor in a plurality of memory cells in the column and a plate line which is coupled to the second electrode plate of said capacitor in every memory cell of the memory block, each memory block further comprising a precharging means for precharging the bit lines to one of first and second voltages which respectively correspond to the two levels of binary data, a plurality of sense amplifiers each of which senses a difference between a reference voltage and a signal voltage developed on a bit line by an accessed memory cell and amplifies the difference voltage to one of said first and second voltages and a balancing means for temporarily keeping the bit lines at an intermediate voltage between said first and second voltages after the amplification of said difference voltage, the memory further comprising a plate line voltage control means for keeping the plate line of each memory block at one of said first and second voltages during standby periods, changing the voltage on the plate line of one of the two memory blocks to the other of said first and second voltages and connecting the plate lines of the two memory blocks during a transition period preceding to an operation period to thereby keep the connected plate lines at said intermediate voltage and disconnecting the plate lines in a standby period following the operation period.
Claim 2
Dependent Claim
362 words
A ferroelectric random-access memory comprising first and second memory blocks each of which comprises a plurality of memory cells arranged in rows and columns, each memory cell comprising a ferroelectric capacitor, which comprises first and second electrode plates and a ferroelectric material interposed between the two electrode plates, and a field effect transistor which is coupled at the source or drain to the first electrode plate of the capacitor, each memory block further comprising a plurality of word lines each of which is arranged along a row of memory cells and is coupled to the gate of said transistor in a plurality of memory cells in the row, a plurality of bit lines each of which is arranged along a column of memory cells and is coupled to the drain or source of said transistor in a plurality of memory cells in the column and a plate line which is coupled to the second electrode plate of said capacitor in every memory cell of the memory block, each memory block further comprising a precharging means for precharging the bit lines to one of first and second voltages which respectively correspond to the two levels of binary data, a plurality of sense amplifiers each of which senses a difference between a reference voltage and a signal voltage developed on a bit line by an accessed memory cell and amplifies the difference voltage to one of said first and second voltages and a balancing means for temporarily keeping the bit lines at an intermediate voltage between said first and second voltages after the amplification of said difference voltage, the memory further comprising a plate line voltage control means for keeping the plate line of each memory block at one of said first and second voltages during standby periods, changing the voltage on the plate line of one of the two memory blocks to the other of said first and second voltages and connecting the plate lines of the two memory blocks during a transition period preceding to an operation period to thereby keep the connected plate lines at said intermediate voltage and disconnecting the plate lines in a standby period following the operation period.
Claim 3
Dependent Claim
19 words
A memory according to claim 1, wherein said first and second voltages are ground potential and supply voltage, respectively.
Claim 4
Dependent Claim
187 words
A memory according to claim 1, wherein a plurality of memory cell pairs each of which is a combination of adjacently positioned first and second memory cells are arranged in rows and columns in each of the first and second memory blocks, each row of said memory cell pairs being provided with a first word line which is coupled to the first memory cells and a second word line which is coupled to the second memory cells, each column of said memory cell pairs being provided with a first bit line which is coupled to the first memory cells and a second bit line which is coupled to the second memory cells, each memory block further comprising, for each column of memory cell pairs, a reference voltage generation means for impressing said reference voltage on one of the first and second bit lines when a memory cell coupled to the other bit line is accessed, in each memory block one of said sense amplifiers being assigned to each column of memory cell pairs to sense and amplify a voltage difference between the first and second bit lines.
Claim 5
Dependent Claim
40 words
A memory according to claim 3, wherein said balancing means is provided to each column of memory cell pairs for connecting the first and second bit lines to temporarily keep the first and second bit lines at said intermediate voltage.
Claim 6
Dependent Claim
38 words
A memory according to claim 1, wherein said plate line voltage control means comprises a voltage stabilizing means for stabilizing said intermediate voltage on the connected plate lines by supplementally supplying the intermediate voltage to the plate lines.
Claim 7
Dependent Claim
34 words
A memory according to claim 1, wherein said plate line voltage control means comprises a field effect transistor of which the source-drain path connects the plate lines of the first and second memory blocks.
Claim 8
Dependent Claim
99 words
A memory according to claim 1, further comprising an auxiliary control means for operating the memory in a volatile mode without causing reversals of the direction of polarization of the ferroelectric material in the capacitors of the respective memory cells, said auxiliary control means comprising an auxiliary precharge means for precharging the bit lines to said intermediate voltage for a predetermined period of time, said plate line voltage control means comprising means for keeping the plate lines of the first and second memory block disconnected and at said first and second voltages, respectively, during operation in the volatile mode.
References Cited (Backward Citations)
US4873664A
Cited
JPH01158691A
Cited
JPH02110895A
Cited
US5086412A
Cited
US5467302A
Cited
US5495440A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-04 | 2000-08-05 | 2001-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-04 | 2004-08-05 | 2005-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-04 | 2008-08-05 | 2009-02-04 | $7700.00 | Window Closed / Lapsed |