US5086412A
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Sense amplifier and method for ferroelectric memory
Assignee: National Semiconductor Corp
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Filing: 1990-11-21
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Granted: 1992-02-04
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Expires: 2010-11-21
Abstract
Abstract A ferroelectric random access memory device contains columns of ferroelectric memory cells, each column of memory cells being coupled to a distinct bit line. Each memory cell is selectively coupled to a corresponding bit line by an access control transistor so that only one memory cell in the column is coupled to the bit line at a time. To read the data stored in a selected memory cell reads, the cell is strobed twice, separately sampling the output voltage generated each time. Since the first read is a destructive read, the second read operation always reads the cell in its "0" state. Then the two sampled outputs are compared, and if the first reading exceeds the second by at least a threshold amount then a "1" output value is generated. Otherwise a "0" is the output value. In a preferred embodiment, the time delay between strobing the memory cell and sampling its output is made longer the first time that the cell is read than for the second time that the cell is read. In this way, if the cell is storing a "0" bit, the first read will produce an output voltage that is smaller than it would have been had the first read not been delayed, which helps to ensure that cells storing "0" bit values are properly sensed.
Inventors
- 👤 James M. Jaffe
- 👤 Norman E. Abt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 10:05
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/22; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
242 words
A ferroelectric random access memory, comprising: at least one column of ferroelectric memory cells, each column of memory cells coupled to a distinct bit line, each memory cell being selectively coupled to said corresponding bit line by an access control transistor so that only one memory cell in said column is coupled to said bit line at a time; control means, coupled to said array of memory cells, for strobing a selected memory cell in said at least one column of memory cells a first time, and then waiting for a predefined period of time before strobing the same selected memory cell a second time; wherein each said strobing of said selected memory cell produces a resulting voltage signal on said bit line coupled to said selected memory cell; a sense amplifier coupled to said bit line and said control means, said sense amplifier including a first sample and hold circuit which samples and holds a data voltage level on said bit line resulting from said first strobing of said selected memory cell, a second sample and hold circuit which samples and holds a reference voltage level on said bit line resulting from said second strobing of said selected memory cell, and a differential amplifier which compares said data voltage level stored in said first sample and hold circuit with said reference voltage level stored in said second sample and hold circuit and generates an output bit value based on said comparison.
Claim 2
Dependent Claim
242 words
A ferroelectric random access memory, comprising: at least one column of ferroelectric memory cells, each column of memory cells coupled to a distinct bit line, each memory cell being selectively coupled to said corresponding bit line by an access control transistor so that only one memory cell in said column is coupled to said bit line at a time; control means, coupled to said array of memory cells, for strobing a selected memory cell in said at least one column of memory cells a first time, and then waiting for a predefined period of time before strobing the same selected memory cell a second time; wherein each said strobing of said selected memory cell produces a resulting voltage signal on said bit line coupled to said selected memory cell; a sense amplifier coupled to said bit line and said control means, said sense amplifier including a first sample and hold circuit which samples and holds a data voltage level on said bit line resulting from said first strobing of said selected memory cell, a second sample and hold circuit which samples and holds a reference voltage level on said bit line resulting from said second strobing of said selected memory cell, and a differential amplifier which compares said data voltage level stored in said first sample and hold circuit with said reference voltage level stored in said second sample and hold circuit and generates an output bit value based on said comparison.
Claim 3
Dependent Claim
67 words
The ferroelectric random access memory of claim 1, wherein said differential amplifier which outputs a first bit value when the data voltage level held in said first sample and hold circuit exceeds the reference voltage level held in said second sample and hold circuit by at least a predefined threshold and which otherwise outputs a second bit value which is the inverse of said first bit value.
Claim 4
Dependent Claim
110 words
The ferroelectric random access memory of claim 1, wherein said first sample and hold circuit samples said data voltage level on said bit line a first predefined amount of time after said first strobing of said selected memory cell, said second sample and hold circuit samples said reference voltage level on said bit line a second predefined amount of time after said second strobing of said selected memory cell, said first predefined amount of time being at least twice as long as said second predefined amount of time; whereby said predefined amounts of time are selected so as to reduce said data voltage level relative to said reference voltage level.
Claim 5
Dependent Claim
31 words
The ferroelectric random access memory of claim 1, wherein said memory includes means for setting said bit line to a predefined voltage prior to each strobing of said selected memory cell.
Claim 6
Dependent Claim
256 words
A ferroelectric random access memory, comprising: an array of ferroelectric memory cells arranged in rows and columns, each column of memory cells being coupled to a distinct bit line, each memory cell being selectively coupled to said corresponding bit line by an access control transistor so that only one memory cell in said column is coupled to said bit line at a time; at least one sense amplifier coupled to one of said bit lines, said sense amplifier including first and second sample and hold means for sampling and holding a voltage level on said bit line, and a differential amplifier which outputs a first bit value when the voltage level held in said first sample and hold means exceeds the voltage level held in said second sample and hold means by at least a predefined threshold and otherwise outputs a second bit value which is the inverse of said first bit value; and control means, coupled to said array of memory cells and said at least one sense amplifier, for strobing a selected memory cell a first time, storing a resulting data voltage level on the bit line coupled to said selected memory cell in said first sample and hold means of said sense amplifier, then strobing said selected memory cell a second time, storing a resulting reference voltage level on the bit line coupled to said selected memory cell in said second sample and hold means of said sense amplifier, and then enabling said differential amplifier so as to generate an output bit value.
Claim 7
Dependent Claim
256 words
A ferroelectric random access memory, comprising: an array of ferroelectric memory cells arranged in rows and columns, each column of memory cells being coupled to a distinct bit line, each memory cell being selectively coupled to said corresponding bit line by an access control transistor so that only one memory cell in said column is coupled to said bit line at a time; at least one sense amplifier coupled to one of said bit lines, said sense amplifier including first and second sample and hold means for sampling and holding a voltage level on said bit line, and a differential amplifier which outputs a first bit value when the voltage level held in said first sample and hold means exceeds the voltage level held in said second sample and hold means by at least a predefined threshold and otherwise outputs a second bit value which is the inverse of said first bit value; and control means, coupled to said array of memory cells and said at least one sense amplifier, for strobing a selected memory cell a first time, storing a resulting data voltage level on the bit line coupled to said selected memory cell in said first sample and hold means of said sense amplifier, then strobing said selected memory cell a second time, storing a resulting reference voltage level on the bit line coupled to said selected memory cell in said second sample and hold means of said sense amplifier, and then enabling said differential amplifier so as to generate an output bit value.
Claim 8
Dependent Claim
110 words
The ferroelectric random access memory of claim 5, wherein said first sample and hold means samples said data voltage level on said bit line a first predefined amount of time after said first strobing of said selected memory cell, said second sample and hold means samples said reference voltage level on said bit line a second predefined amount of time after said second strobing of said selected memory cell, said first predefined amount of time being at least twice as long as said second predefined amount of time; whereby said predefined amounts of time are selected so as to reduce said data voltage level relative to said reference voltage level.
Claim 9
Dependent Claim
31 words
The ferroelectric random access memory of claim 5, wherein said memory includes means for setting said bit line to a predefined voltage prior to each strobing of said selected memory cell.
Claim 10
Independent Claim
232 words
A method of operating a ferroelectric random access memory, said memory containing an array of ferroelectric memory cells arranged in columns, each column of memory cells being coupled to a distinct bit line, each memory cell being selectively coupled to said corresponding bit line by an access control transistor so that only one memory cell in said column is coupled to said bit line at a time; the steps of the method comprising: selecting a memory cell in at least one of said columns of memory cells by enabling said memory cell's access control transistor and thereby coupling said selected memory cell to a bit line; strobing said selected memory cell so as to produce a data voltage level on said bit line indicative of data stored in said selected memory cell; sampling and holding said voltage level on said bit line in a first sample and hold circuit; strobing said selected memory cell a second time so as to produce a reference voltage level on said bit line indicative of device characteristics of said selected memory cell; sampling and holding said reference voltage level on said bit line in a second sample and hold circuit; comparing said data voltage level stored in said first sample and hold circuit with said reference voltage level stored in said second sample and hold circuit, and generating an output bit value based on said comparison.
Claim 11
Independent Claim
232 words
A method of operating a ferroelectric random access memory, said memory containing an array of ferroelectric memory cells arranged in columns, each column of memory cells being coupled to a distinct bit line, each memory cell being selectively coupled to said corresponding bit line by an access control transistor so that only one memory cell in said column is coupled to said bit line at a time; the steps of the method comprising: selecting a memory cell in at least one of said columns of memory cells by enabling said memory cell's access control transistor and thereby coupling said selected memory cell to a bit line; strobing said selected memory cell so as to produce a data voltage level on said bit line indicative of data stored in said selected memory cell; sampling and holding said voltage level on said bit line in a first sample and hold circuit; strobing said selected memory cell a second time so as to produce a reference voltage level on said bit line indicative of device characteristics of said selected memory cell; sampling and holding said reference voltage level on said bit line in a second sample and hold circuit; comparing said data voltage level stored in said first sample and hold circuit with said reference voltage level stored in said second sample and hold circuit, and generating an output bit value based on said comparison.
Claim 12
Dependent Claim
72 words
The method of operating a ferroelectric random access memory set forth in claim 8, said comparing and generating steps generating a first bit value when the data voltage level held in said first sample and hold circuit exceeds the reference voltage level held in said second sample and hold circuit by at least a predefined threshold and otherwise outputs a second bit value which is the inverse of said first bit value.
Claim 13
Dependent Claim
90 words
The method of operating a ferroelectric random access memory set forth in claim 8, wherein said first sampling step is performed a first predefined amount of time after said first strobing step; said second sampling step is performed a second predefined amount of time after said second strobing step; said first predefined amount of time being at least twice as long as said second predefined amount of time; whereby said predefined amounts of time are selected so as to reduce said data voltage level relative to said reference voltage level.
Claim 14
Dependent Claim
33 words
The method of operating a ferroelectric random access memory set forth in claim 8, further including the step of setting said bit line to a predefined voltage prior to each said strobing step.
References Cited (Backward Citations)
US3651494A
Cited
US4888733A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-02-03 | 1995-08-05 | 1996-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-02-03 | 1999-08-05 | 2000-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-02-03 | 2003-08-05 | 2004-02-04 | $7700.00 | Window Closed / Lapsed |