US6498362B1
Expired / Lapsed
US
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Weak ferroelectric transistor
Assignee: Micron Technology Inc
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Filing: 1999-08-26
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Granted: 2002-12-24
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Expires: 2019-08-26
Abstract
Abstract Field effect transistors having a ferroelectric layer overlying a gate insulator layer as well as methods of their formation and use, and devices produced therefrom. Such ferroelectric field effect transistors are suitable for use in memory devices as the polarization of the ferroelectric layer can represent distinct logic states. The polarization of the ferroelectric layer alters the threshold voltage of the field effect transistor thus producing distinctly different conductivity states through the weak ferroelectric transistor at a given gate potential depending upon the polarization. The ferroelectric layer may contain a weak ferroelectric material having spontaneous polarization values in the range of approximately 0.01 μCoulomb/cm 2 to 1 μCoulomb/cm 2 . The ferroelectric layer may contain a doped zinc oxide material doped with lithium and/or magnesium. Such weak ferroelectric materials permit effective transistor operation without the need for a programming conductor interposed between the ferroelectric layer and the gate insulator layer. This is possible because effective programming voltages can be applied across the ferroelectric layer and the gate insulator layer in series without exceeding the breakdown voltage of the gate insulator layer. Furthermore, having a gate insulator layer interposed between a substrate and the ferroelectric material eliminates the undesirable surface interfaces and surface states resulting from a silicon substrate-ferroelectric interface.
Inventors
- 👤 Leonard Forbes
- 👤 Kie Y. Ahn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:36
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/689; H10D30/00; H10D30/60; H10D30/701; H10D64/01; H10D64/031; H10D64/033
Claims Analysis
Total Claims: 72
Claim 1
Independent Claim
82 words
A field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying and adjacent the gate insulator layer, wherein the ferroelectric layer comprises a weak ferroelectric material having a spontaneous polarization in the range of approximately 0.01 μCoulomb/cm 2 to approximately 1 μCoulomb/cm 2 , wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is approximately 10 times the thickness of the gate insulator layer.
Claim 2
Dependent Claim
82 words
A field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying and adjacent the gate insulator layer, wherein the ferroelectric layer comprises a weak ferroelectric material having a spontaneous polarization in the range of approximately 0.01 μCoulomb/cm 2 to approximately 1 μCoulomb/cm 2 , wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is approximately 10 times the thickness of the gate insulator layer.
Claim 3
Dependent Claim
49 words
The field effect transistor of claim 1 , wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is less than approximately 10,000 Å and the thickness of the gate insulator layer is less than approximately 1,000 Å.
Claim 4
Dependent Claim
60 words
The field effect transistor of claim 1 , wherein the thickness of at least one of the gate insulator layer and the ferroelectric layer is adjusted such that a programming voltage applied across the gate insulator layer and the ferroelectric layer in series is sufficient to polarize the ferroelectric layer without exceeding a breakdown voltage of the gate insulator layer.
Claim 5
Dependent Claim
130 words
The field effect transistor of claim 1 , further comprising: a source region in the substrate, a drain region in the substrate and separated from the source region by a channel region; and an upper conductor layer overlying the ferroelectric layer; wherein a programming voltage applied across the upper conductor layer to a region selected from the group consisting of the source region and the drain region is capable of polarizing the weak ferroelectric material, thereby producing a polarization state in the ferroelectric layer; and wherein a second voltage having a lower magnitude than the programming voltage and applied to the upper conductor layer is capable of producing distinctly different conductivity states between the source region and the drain region in response to the polarization state of the ferroelectric layer.
Claim 6
Dependent Claim
94 words
A field effect transistor, comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying the gate insulator layer and without a programming conductor interposed between the ferroelectric layer and the gate insulator layer, wherein the ferroelectric layer comprises a weak ferroelectric material having a spontaneous polarization in the range of approximately 0.01 μCoulomb/cm 2 to approximately 1 μCoulomb/cm 2 , wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is 10 times the thickness of the gate insulator layer.
Claim 7
Dependent Claim
94 words
A field effect transistor, comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying the gate insulator layer and without a programming conductor interposed between the ferroelectric layer and the gate insulator layer, wherein the ferroelectric layer comprises a weak ferroelectric material having a spontaneous polarization in the range of approximately 0.01 μCoulomb/cm 2 to approximately 1 μCoulomb/cm 2 , wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is 10 times the thickness of the gate insulator layer.
Claim 8
Dependent Claim
83 words
A field effect transistor, comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying and adjacent the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x Li 1-x O where x ranges from approximately 0.70 to approximately 0.99, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer.
Claim 9
Dependent Claim
83 words
A field effect transistor, comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying and adjacent the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x Li 1-x O where x ranges from approximately 0.70 to approximately 0.99, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer.
Claim 10
Dependent Claim
96 words
A field effect transistor, comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying the gate insulator layer and without a programming conductor interposed between the ferroelectric layer and the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x Li 1-x O where x ranges from approximately 0.70 to approximately 0.99, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer.
Claim 11
Dependent Claim
96 words
A field effect transistor, comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying the gate insulator layer and without a programming conductor interposed between the ferroelectric layer and the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x Li 1-x O where x ranges from approximately 0.70 to approximately 0.99, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer.
Claim 12
Dependent Claim
83 words
A field effect transistor, comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying and adjacent the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x Mg 1-x O where x ranges from approximately 0.70 to approximately 0.99, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer.
Claim 13
Dependent Claim
83 words
A field effect transistor, comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying and adjacent the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x Mg 1-x O where x ranges from approximately 0.70 to approximately 0.99, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer.
Claim 14
Dependent Claim
96 words
A field effect transistor, comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying the gate insulator layer and without a programming conductor interposed between the ferroelectric layer and the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x Mg 1-x O where x ranges from approximately 0.70 to approximately 0.99, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer.
Claim 15
Dependent Claim
96 words
A field effect transistor, comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying the gate insulator layer and without a programming conductor interposed between the ferroelectric layer and the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x Mg 1-x O where x ranges from approximately 0.70 to approximately 0.99, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer.
Claim 16
Dependent Claim
109 words
A field effect transistor, comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying and adjacent the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x (Li y Mg z )O where x ranges from approximately 0.70 to approximately 0.99, y and z each independently range from approximately 0.00 to approximately 0.30 and the sum of y+z ranges from approximately 0.01 to approximately 0.30, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of tie ferroelectric layer is greater than the thickness of the gate insulator layer.
Claim 17
Dependent Claim
109 words
A field effect transistor, comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying and adjacent the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x (Li y Mg z )O where x ranges from approximately 0.70 to approximately 0.99, y and z each independently range from approximately 0.00 to approximately 0.30 and the sum of y+z ranges from approximately 0.01 to approximately 0.30, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of tie ferroelectric layer is greater than the thickness of the gate insulator layer.
Claim 18
Dependent Claim
40 words
The field effect transistor of claim 10 , wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is approximately 10 times the thickness of the gate insulator layer.
Claim 19
Dependent Claim
41 words
The field effect transistor of claim 10 , wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is at least 5 times the thickness of the gate insulator layer.
Claim 20
Dependent Claim
49 words
The field effect transistor of claim 10 , wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is less than approximately 10,000 Å and the thickness of the gate insulator layer is less than approximately 1,000 Å.
Claim 21
Dependent Claim
60 words
The field effect transistor of claim 10 , wherein the thickness of at least one of the gate insulator layer and the ferroelectric layer is adjusted such that a programming voltage applied across the gate insulator layer and the ferroelectric layer in series is sufficient to polarize the ferroelectric layer without exceeding a breakdown voltage of the gate insulator layer.
Claim 22
Dependent Claim
130 words
The field effect transistor of claim 10 , further comprising: a source region in the substrate; a drain region in the substrate and separated from the source region by a channel region; and an upper conductor layer overlying the ferroelectric layer; wherein a programming voltage applied across the upper conductor layer to a region selected from the group consisting of the source region and the drain region is capable of polarizing the weak ferroelectric material, thereby producing a polarization state in the ferroelectric layer; and wherein a second voltage having a lower magnitude than the programming voltage and applied to the upper conductor layer is capable of producing distinctly different conductivity states between the source region and the drain region in response to the polarization state of the ferroelectric layer.
Claim 23
Dependent Claim
122 words
A field effect transistor, comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying the gate insulator layer and without a programming conductor interposed between the ferroelectric layer and the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x (Li y Mg z )O where x ranges from approximately 0.70 to approximately 0.99, y and z each independently range from approximately 0.00 to approximately 0.30 and the sum of y+z ranges from approximately 0.01 to approximately 0.30, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer.
Claim 24
Dependent Claim
122 words
A field effect transistor, comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying the gate insulator layer and without a programming conductor interposed between the ferroelectric layer and the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x (Li y Mg z )O where x ranges from approximately 0.70 to approximately 0.99, y and z each independently range from approximately 0.00 to approximately 0.30 and the sum of y+z ranges from approximately 0.01 to approximately 0.30, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer.
Claim 25
Dependent Claim
116 words
A semiconductor die, comprising: an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying and adjacent the gate insulator layer, wherein the ferroelectric layer comprises a weak ferroelectric material having a spontaneous polarization in the range of approximately 0.01 μCoulomb/cm 2 to approximately 1 μCoulomb/cm 2 , wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer.
Claim 26
Dependent Claim
116 words
A semiconductor die, comprising: an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying and adjacent the gate insulator layer, wherein the ferroelectric layer comprises a weak ferroelectric material having a spontaneous polarization in the range of approximately 0.01 μCoulomb/cm 2 to approximately 1 μCoulomb/cm 2 , wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer.
Claim 27
Dependent Claim
44 words
The semiconductor die of claim 17 , wherein is adjusted such that a programming voltage applied across the gate insulator layer and the ferroelectric layer in series is sufficient to polarize the ferroelectric layer without exceeding a breakdown voltage of the gate insulator layer.
Claim 28
Dependent Claim
134 words
The semiconductor die of claim 17 , wherein the field effect transistor further comprises: a source region in the substrate, a drain region in the substrate and separated from the source region by a channel region; and an upper conductor layer overlying the ferroelectric layer; wherein a programming voltage applied across the upper conductor layer to a region selected from the group consisting of the source region and the drain region is capable of polarizing the weak ferroelectric material, thereby producing a polarization state in the ferroelectric layer; and wherein a second voltage having a lower magnitude than the programming voltage and applied to the upper conductor layer is capable of producing distinctly different conductivity states between the source region and the drain region in response to the polarization state of the ferroelectric layer.
Claim 29
Dependent Claim
129 words
A semiconductor die, comprising: an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying the gate insulator layer and without a programming conductor interposed between the ferroelectric layer and the gate insulator layer, wherein the ferroelectric layer comprises a weak ferroelectric material having a spontaneous polarization in the range of approximately 0.01 μCoulomb/cm 2 to approximately 1 μCoulomb/cm 2 , wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer.
Claim 30
Dependent Claim
129 words
A semiconductor die, comprising: an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying the gate insulator layer and without a programming conductor interposed between the ferroelectric layer and the gate insulator layer, wherein the ferroelectric layer comprises a weak ferroelectric material having a spontaneous polarization in the range of approximately 0.01 μCoulomb/cm 2 to approximately 1 μCoulomb/cm 2 , wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer.
Claim 31
Dependent Claim
118 words
A semiconductor die, comprising; an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying and adjacent the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x Li 1-x O where x ranges from approximately 0.70 to approximately 0.99, wherein the gate insulator layer and the feoelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer.
Claim 32
Dependent Claim
118 words
A semiconductor die, comprising; an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying and adjacent the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x Li 1-x O where x ranges from approximately 0.70 to approximately 0.99, wherein the gate insulator layer and the feoelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer.
Claim 33
Dependent Claim
131 words
A semiconductor die, comprising: an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying the gate insulator layer and without a programming conductor interposed between the ferroelectric layer and the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x Li 1-x O where x ranges from approximately 0.70 to approximately 0.99, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer.
Claim 34
Dependent Claim
131 words
A semiconductor die, comprising: an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying the gate insulator layer and without a programming conductor interposed between the ferroelectric layer and the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x Li 1-x O where x ranges from approximately 0.70 to approximately 0.99, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer.
Claim 35
Dependent Claim
118 words
A semiconductor die, comprising: an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying and adjacent the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x Mg 1-x O where x ranges from approximately 0.70 to approximately 0.99, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer.
Claim 36
Dependent Claim
118 words
A semiconductor die, comprising: an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying and adjacent the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x Mg 1-x O where x ranges from approximately 0.70 to approximately 0.99, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer.
Claim 37
Dependent Claim
132 words
A semiconductor die, comprising: an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying the gate insulator layer and without a programming conductor interposed between the ferroelectric layer and the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x Mg 1-x O where x ranges from approximately 0.70 to approximately 0.99, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is approximately 10 times the thickness of the gate insulator layer.
Claim 38
Dependent Claim
132 words
A semiconductor die, comprising: an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying the gate insulator layer and without a programming conductor interposed between the ferroelectric layer and the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x Mg 1-x O where x ranges from approximately 0.70 to approximately 0.99, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is approximately 10 times the thickness of the gate insulator layer.
Claim 39
Dependent Claim
144 words
A semiconductor die, comprising: an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying and adjacent the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x (Li y Mg z )O where x ranges from approximately 0.70 to approximately 0.99, y and z each independently range from approximately 0.00 to approximately 0.30 and the sum of y+z ranges from approximately 0.01 to approximately 0.30, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer.
Claim 40
Dependent Claim
144 words
A semiconductor die, comprising: an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying and adjacent the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x (Li y Mg z )O where x ranges from approximately 0.70 to approximately 0.99, y and z each independently range from approximately 0.00 to approximately 0.30 and the sum of y+z ranges from approximately 0.01 to approximately 0.30, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer.
Claim 41
Dependent Claim
74 words
The semiconductor die of claim 25 , wherein the gate insulator layer and the ferroelectric layer of the field effect transistor each have a thickness and wherein the thickness of the gate insulator layer and the ferroelectric layer are adjusted such that a programming voltage applied across the gate insulator layer and the ferroelectric layer in series is sufficient to polarize the ferroelectric layer without exceeding a breakdown voltage of the gate insulator layer.
Claim 42
Dependent Claim
134 words
The semiconductor die of claim 25 , wherein the field effect transistor farther comprises: a source region in the substrate; a drain region in the substrate and separated from the source region by a channel region; and an upper conductor layer overlying the ferroelectric layer; wherein a programming voltage applied across the upper conductor layer to a region selected from the group consisting of the source region and the drain region is capable of polarizing the weak ferroelectric material, thereby producing a polarization state in the ferroelectric layer; and wherein a second voltage having a lower magnitude than the programming voltage and applied to the upper conductor layer is capable of producing distinctly different conductivity states between the source region and the drain region in response to the polarization state of the ferroelectric layer.
Claim 43
Dependent Claim
157 words
A semiconductor die, comprising: an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying the gate insulator layer and without a programming conductor interposed between the ferroelectric layer and the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x (Li y Mg z )O where x ranges from approximately 0.70 to approximately 0.99, y and z each independently range from approximately 0.00 to approximately 0.30 and the sum of y+z ranges from approximately 0.01 to approximately 0.30, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer.
Claim 44
Dependent Claim
157 words
A semiconductor die, comprising: an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying the gate insulator layer and without a programming conductor interposed between the ferroelectric layer and the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x (Li y Mg z )O where x ranges from approximately 0.70 to approximately 0.99, y and z each independently range from approximately 0.00 to approximately 0.30 and the sum of y+z ranges from approximately 0.01 to approximately 0.30, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer.
Claim 45
Dependent Claim
139 words
A memory device, comprising: an array of memory cells, wherein at least one memory cell comprises a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying and adjacent the gate insulator layer, wherein the ferroelectric layer comprises a weak ferroelectric material having A spontaneous polarization in the range of approximately 0.01 μCoulomb/cm 2 to approximately 1 μCoulomb/cm 2 , wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer; a row access circuit coupled to the array of memory cells; a column access circuit coupled to the array of memory cells; and an address decoder circuit coupled to the row access circuit and the column access circuit.
Claim 46
Dependent Claim
139 words
A memory device, comprising: an array of memory cells, wherein at least one memory cell comprises a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying and adjacent the gate insulator layer, wherein the ferroelectric layer comprises a weak ferroelectric material having A spontaneous polarization in the range of approximately 0.01 μCoulomb/cm 2 to approximately 1 μCoulomb/cm 2 , wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer; a row access circuit coupled to the array of memory cells; a column access circuit coupled to the array of memory cells; and an address decoder circuit coupled to the row access circuit and the column access circuit.
Claim 47
Dependent Claim
74 words
The memory device of claim 29 , wherein the gate insulator layer and the ferroelectric layer of the field effect transistor each have a thickness and wherein the thickness of the gate insulator layer and the ferroelectric layer are adjusted such that a programming voltage applied across the gate insulator layer and the ferroelectric layer in series is sufficient to polarize the ferroelectric layer without exceeding a breakdown voltage of the gate insulator layer.
Claim 48
Dependent Claim
134 words
The memory device of claim 29 , wherein the field effect transistor further comprises: a source region in the substrate; a drain region in the substrate and separated from the source region by a channel region; and an upper conductor layer overlying the ferroelectric layer; wherein a programming voltage applied across the upper conductor layer to a region selected from the group consisting of the source region and the drain region is capable of polarizing the weak ferroelectric material, thereby producing a polarization state in the ferroelectric layer; and wherein a second voltage having a lower magnitude than the programming voltage and applied to the upper conductor layer is capable of producing distinctly different conductivity states between the source region and the drain region in response to the polarization state of the ferroelectric layer.
Claim 49
Dependent Claim
154 words
A memory device, comprising: an array of memory cells, wherein at least one memory cell composes a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying the gate insulator layer and without a programming conductor interposed between the ferroelectric layer and the gate insulator layer, wherein the ferroelectric layer comprises a weak ferroelectric material having a spontaneous polarization in the range of approximately 0.01 μCoulomb/cm 2 to approximately 1 μCoulomb/cm 2 , wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is 10 times greater than the thickness of the gate insulator layer; a row access circuit coupled to the array of memory cells; a column access circuit coupled to the array of memory cells; and an address decoder circuit coupled to the row access circuit and the column access circuit.
Claim 50
Dependent Claim
154 words
A memory device, comprising: an array of memory cells, wherein at least one memory cell composes a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying the gate insulator layer and without a programming conductor interposed between the ferroelectric layer and the gate insulator layer, wherein the ferroelectric layer comprises a weak ferroelectric material having a spontaneous polarization in the range of approximately 0.01 μCoulomb/cm 2 to approximately 1 μCoulomb/cm 2 , wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is 10 times greater than the thickness of the gate insulator layer; a row access circuit coupled to the array of memory cells; a column access circuit coupled to the array of memory cells; and an address decoder circuit coupled to the row access circuit and the column access circuit.
Claim 51
Dependent Claim
169 words
A memory device, comprising; an array of memory cells, wherein at least one memory cell comprises a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying and adjacent the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x (Li y Mg z )O where, x ranges from approximately 0.70 to approximately 0.99, y and z each independently range from approximately 0.00 to approximately 0.30 and the sum of y+z ranges from approximately 0.01 to approximately 0.30, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is 10 times greater than the thickness of the gate insulator layer; a row access circuit coupled to the array of memory cells; a column access circuit coupled to the array of memory cells; and an address decoder circuit coupled to the row access circuit and the column access circuit.
Claim 52
Dependent Claim
169 words
A memory device, comprising; an array of memory cells, wherein at least one memory cell comprises a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying and adjacent the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x (Li y Mg z )O where, x ranges from approximately 0.70 to approximately 0.99, y and z each independently range from approximately 0.00 to approximately 0.30 and the sum of y+z ranges from approximately 0.01 to approximately 0.30, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is 10 times greater than the thickness of the gate insulator layer; a row access circuit coupled to the array of memory cells; a column access circuit coupled to the array of memory cells; and an address decoder circuit coupled to the row access circuit and the column access circuit.
Claim 53
Dependent Claim
74 words
The memory device of claim 33 , wherein the gate insulator layer and the ferroelectric layer of the field effect transistor each have a thickness and wherein the thickness of the gate insulator layer and the ferroelectric layer are adjusted such that a programming voltage applied across the gate insulator layer and the ferroelectric layer in series is sufficient to polarize the ferroelectric layer without exceeding a breakdown voltage of the gate insulator layer.
Claim 54
Dependent Claim
134 words
The memory device of claim 33 , wherein the field effect transistor further comprises: a source region in the substrate; a drain region in the substrate and separated from the source region by a channel region; and an upper conductor layer overlying the ferroelectric layer; wherein a programming voltage applied across the upper conductor layer to a region selected from the group consisting of the source region and the drain region is capable of polarizing the weal ferroelectric material, thereby producing a polarization state in the ferroelectric layer; and wherein a second voltage having a lower magnitude than the programming voltage and applied to the upper conductor layer is capable of producing distinctly different conductivity states between the source region and the drain region in response to the polarization state of the ferroelectric layer.
Claim 55
Dependent Claim
182 words
A memory device, comprising: an array of memory cells, wherein at least one memory cell comprises a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying the gate insulator layer and without a programming conductor interposed between the ferroelectric layer and the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x (Li y Mg z )O where x ranges from approximately 0.70 to approximately 0.99, y and z each independently range from approximately 0.00 to approximately 0.30 and the sum of y+z ranges from approximately 0.01 to approximately 0.30, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is 10 times greater than the thickness of the gate insulator layer; a row access circuit coupled to the array of memory cells; a column access circuit coupled to the array of memory cells; and an address decoder circuit coupled to the row access circuit and the column access circuit.
Claim 56
Dependent Claim
182 words
A memory device, comprising: an array of memory cells, wherein at least one memory cell comprises a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying the gate insulator layer and without a programming conductor interposed between the ferroelectric layer and the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x (Li y Mg z )O where x ranges from approximately 0.70 to approximately 0.99, y and z each independently range from approximately 0.00 to approximately 0.30 and the sum of y+z ranges from approximately 0.01 to approximately 0.30, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is 10 times greater than the thickness of the gate insulator layer; a row access circuit coupled to the array of memory cells; a column access circuit coupled to the array of memory cells; and an address decoder circuit coupled to the row access circuit and the column access circuit.
Claim 57
Dependent Claim
208 words
A memory module, comprising: a support; a plurality of leads extending from the support; a command link coupled to at least one of the plurality of leads; a plurality of data links, wherein each data link is coupled to at least one of the plurality of leads; and at least one memory device contained on the support and coupled to the command link, wherein the at least one memory device comprises: an array of memory cells, wherein at least one memory cell comprises a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying and adjacent the gate insulator layer, wherein the ferroelectric layer comprises a weak ferroelectric material having a spontaneous polarization in the range of approximately 0.01 μCoulomb/cm 2 to approximately 1 μCoulomb/cm 2 , wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is 10 times greater than the thickness of the gate insulator layer; a row access circuit coupled to the array of memory cells; a column access circuit coupled to the array of memory cells; and an address decoder circuit coupled to the row access circuit and the column access circuit.
Claim 58
Dependent Claim
208 words
A memory module, comprising: a support; a plurality of leads extending from the support; a command link coupled to at least one of the plurality of leads; a plurality of data links, wherein each data link is coupled to at least one of the plurality of leads; and at least one memory device contained on the support and coupled to the command link, wherein the at least one memory device comprises: an array of memory cells, wherein at least one memory cell comprises a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying and adjacent the gate insulator layer, wherein the ferroelectric layer comprises a weak ferroelectric material having a spontaneous polarization in the range of approximately 0.01 μCoulomb/cm 2 to approximately 1 μCoulomb/cm 2 , wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is 10 times greater than the thickness of the gate insulator layer; a row access circuit coupled to the array of memory cells; a column access circuit coupled to the array of memory cells; and an address decoder circuit coupled to the row access circuit and the column access circuit.
Claim 59
Dependent Claim
221 words
A memory module, comprising: a support; a plurality of leads extending from the support; a command link coupled to at least one of the plurality of leads; a plurality of data links, wherein each data link is coupled to at least one of the plurality of leads; and at least one memory device contained on the support and coupled to the command link, wherein the at least one memory device comprises: an array of memory cells, wherein at least one memory cell comprises a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying the gate insulator layer and without a programming conductor interposed between the ferroelectric layer and the gate insulator layer, wherein the ferroelectric layer comprises a weak ferroelectric material having a spontaneous polarization in the range of approximately 0.01 μCoulomb/cm 2 to approximately 1 μCoulomb/cm 2 , wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is 10 times greater than the thickness of the gate insulator layer; a row access circuit coupled to the array of memory cells; a column access circuit coupled to the array of memory cells; and an address decoder circuit coupled to the row access circuit and the column access circuit.
Claim 60
Dependent Claim
221 words
A memory module, comprising: a support; a plurality of leads extending from the support; a command link coupled to at least one of the plurality of leads; a plurality of data links, wherein each data link is coupled to at least one of the plurality of leads; and at least one memory device contained on the support and coupled to the command link, wherein the at least one memory device comprises: an array of memory cells, wherein at least one memory cell comprises a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying the gate insulator layer and without a programming conductor interposed between the ferroelectric layer and the gate insulator layer, wherein the ferroelectric layer comprises a weak ferroelectric material having a spontaneous polarization in the range of approximately 0.01 μCoulomb/cm 2 to approximately 1 μCoulomb/cm 2 , wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is 10 times greater than the thickness of the gate insulator layer; a row access circuit coupled to the array of memory cells; a column access circuit coupled to the array of memory cells; and an address decoder circuit coupled to the row access circuit and the column access circuit.
Claim 61
Dependent Claim
234 words
A memory module, comprising: a support; a plurality of leads extending from the support; a command link coupled to at least one of the plurality of leads; a plurality of data links, wherein each data link is coupled to at least one of the plurality of leads; and at least one memory device contained on the support and coupled to the command link, wherein the at least one memory device comprises: an array of memory cells, wherein at least one memory cell comprises a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying and adjacent the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x (Li y Mg z )O where x ranges from approximately 0.70 to approximately 0.99, y and z each independently range from approximately 0.00 to approximately 0.30 and the sum of y+z ranges from approximately 0.01 to approximately 0.30, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer; a row access circuit coupled to the array of memory cells; a column access circuit coupled to the array of memory cells; and an address decoder circuit coupled to the row access circuit and the column access circuit.
Claim 62
Dependent Claim
234 words
A memory module, comprising: a support; a plurality of leads extending from the support; a command link coupled to at least one of the plurality of leads; a plurality of data links, wherein each data link is coupled to at least one of the plurality of leads; and at least one memory device contained on the support and coupled to the command link, wherein the at least one memory device comprises: an array of memory cells, wherein at least one memory cell comprises a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying and adjacent the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x (Li y Mg z )O where x ranges from approximately 0.70 to approximately 0.99, y and z each independently range from approximately 0.00 to approximately 0.30 and the sum of y+z ranges from approximately 0.01 to approximately 0.30, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer; a row access circuit coupled to the array of memory cells; a column access circuit coupled to the array of memory cells; and an address decoder circuit coupled to the row access circuit and the column access circuit.
Claim 63
Dependent Claim
247 words
A memory module, comprising: a support; a plurality of leads extending from the support; a command link coupled to at least one of the plurality of leads; a plurality of data links, wherein each data link is coupled to at least one of the plurality of leads; and at least one memory device contained on the support and coupled to the command link, wherein the at least one memory device comprises: an array of memory cells, wherein at least one memory cell comprises a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying the gate insulator layer and without a programming conductor interposed between the ferroelectric layer and the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x (Li y Mg z )O where x ranges from approximately 0.70 to approximately 0.99, y and z each independently range from approximately 0.00 to approximately 0.30 and the sum of y+z ranges from approximately 0.01 to approximately 0.30, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer; a row access circuit coupled to the array of memory cells; a column access circuit coupled to the array of memory cells; and an address decoder circuit coupled to the row access circuit and the column access circuit.
Claim 64
Dependent Claim
247 words
A memory module, comprising: a support; a plurality of leads extending from the support; a command link coupled to at least one of the plurality of leads; a plurality of data links, wherein each data link is coupled to at least one of the plurality of leads; and at least one memory device contained on the support and coupled to the command link, wherein the at least one memory device comprises: an array of memory cells, wherein at least one memory cell comprises a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying the gate insulator layer and without a programming conductor interposed between the ferroelectric layer and the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x (Li y Mg z )O where x ranges from approximately 0.70 to approximately 0.99, y and z each independently range from approximately 0.00 to approximately 0.30 and the sum of y+z ranges from approximately 0.01 to approximately 0.30, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater than the thickness of the gate insulator layer; a row access circuit coupled to the array of memory cells; a column access circuit coupled to the array of memory cells; and an address decoder circuit coupled to the row access circuit and the column access circuit.
Claim 65
Dependent Claim
148 words
An electronic system, comprising: a processor; and a circuit module having a plurality of leads coupled to the processor, and further having a semiconductor die coupled to the plurality of leads, wherein the semiconductor die comprises: an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying and adjacent the gate insulator layer, wherein the ferroelectric layer comprises a weak ferroelectric material having a spontaneous polarization in the range of approximately 0.01 μCoulomb/cm 2 to approximately 1 μCoulomb/cm 2 , wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater then the thickness of the gate insulator layer.
Claim 66
Dependent Claim
148 words
An electronic system, comprising: a processor; and a circuit module having a plurality of leads coupled to the processor, and further having a semiconductor die coupled to the plurality of leads, wherein the semiconductor die comprises: an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying and adjacent the gate insulator layer, wherein the ferroelectric layer comprises a weak ferroelectric material having a spontaneous polarization in the range of approximately 0.01 μCoulomb/cm 2 to approximately 1 μCoulomb/cm 2 , wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is greater then the thickness of the gate insulator layer.
Claim 67
Dependent Claim
159 words
An electronic system, comprising: a processor; and a circuit module having a plurality of leads coupled to the processor, and further having a semiconductor die coupled to the plurality of leads, wherein the semiconductor die comprises: an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a field effect transistor, the field effect transistor comprising: gate insulator layer overlying a substrate; and a ferroelectric layer overlying the gate insulator layer and without a programming conductor interposed between the feoelectric layer and the gate insulator layer, wherein the ferroelectric layer comprises a weak ferroelectric material having a spontaneous polarization in the range of approximately 0.01 μCoulomb/cm 2 to approximately 1 μCoulomb/cm 2 , wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer greater than the thickness of the gate insulator layer.
Claim 68
Dependent Claim
159 words
An electronic system, comprising: a processor; and a circuit module having a plurality of leads coupled to the processor, and further having a semiconductor die coupled to the plurality of leads, wherein the semiconductor die comprises: an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a field effect transistor, the field effect transistor comprising: gate insulator layer overlying a substrate; and a ferroelectric layer overlying the gate insulator layer and without a programming conductor interposed between the feoelectric layer and the gate insulator layer, wherein the ferroelectric layer comprises a weak ferroelectric material having a spontaneous polarization in the range of approximately 0.01 μCoulomb/cm 2 to approximately 1 μCoulomb/cm 2 , wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer greater than the thickness of the gate insulator layer.
Claim 69
Dependent Claim
178 words
An electronic system, comprising: a processor; and a circuit module having a plurality of leads coupled to the processor, and further having a semiconductor die coupled to the plurality of leads, wherein the semiconductor die comprises: an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying and adjacent the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x (Li y Mg z )O where x ranges from approximately 0.70 to approximately 0.99, y and z each independently range from approximately 0.00 to approximately 0.30 and the sum of y+z ranges from approximately 0.01 to approximately 0.30, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is 10 times greater than the thickness of the gate insulator layer.
Claim 70
Dependent Claim
178 words
An electronic system, comprising: a processor; and a circuit module having a plurality of leads coupled to the processor, and further having a semiconductor die coupled to the plurality of leads, wherein the semiconductor die comprises: an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a field effect transistor, the field effect transistor comprising: a gate insulator layer overlying a substrate; and a ferroelectric layer overlying and adjacent the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x (Li y Mg z )O where x ranges from approximately 0.70 to approximately 0.99, y and z each independently range from approximately 0.00 to approximately 0.30 and the sum of y+z ranges from approximately 0.01 to approximately 0.30, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is 10 times greater than the thickness of the gate insulator layer.
Claim 71
Dependent Claim
191 words
An electronic system, comprising: a processor; and a circuit module having a plurality of leads coupled to the processor, and further having a semiconductor die coupled to the plurality of leads, wherein the semiconductor die comprises: an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a field effect transistor, the field effect transistor comprising; a gate insulator layer overlying a substrate; and a ferroelectric layer overlying the gate insulator layer and without a programming conductor interposed between the ferroelectric layer and the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x (Li y Mg z )O where x ranges from approximately 0.70 to approximately 0.99, y and z each independently range from approximately 0.00 to approximately 0.30 and the sum of y+z ranges from approximately 0.01 to approximately 0.30, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is 10 times greater than the thickness of the gate insulator layer.
Claim 72
Dependent Claim
191 words
An electronic system, comprising: a processor; and a circuit module having a plurality of leads coupled to the processor, and further having a semiconductor die coupled to the plurality of leads, wherein the semiconductor die comprises: an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a field effect transistor, the field effect transistor comprising; a gate insulator layer overlying a substrate; and a ferroelectric layer overlying the gate insulator layer and without a programming conductor interposed between the ferroelectric layer and the gate insulator layer, wherein the ferroelectric layer comprises a doped zinc oxide material having a general formula of Zn x (Li y Mg z )O where x ranges from approximately 0.70 to approximately 0.99, y and z each independently range from approximately 0.00 to approximately 0.30 and the sum of y+z ranges from approximately 0.01 to approximately 0.30, wherein the gate insulator layer and the ferroelectric layer each have a thickness and wherein the thickness of the ferroelectric layer is 10 times greater than the thickness of the gate insulator layer.
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