US6151241A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Ferroelectric memory with disturb protection
Assignee: Panasonic Holdings Corp
•
Filing: 1999-05-19
•
Granted: 2000-11-21
•
Expires: 2019-05-19
Abstract
Abstract A ferroelectric field effect transistor memory cell includes a thin film varistor located between the gate electrode and the ferroelectric layer. The varistor protects the ferroelectric layer from disturb voltage pulses arising from memory read, write and sense operations. A second electrode is located between the thin film varistor and the ferroelectric layer. The thin film ferroelectric is positioned over the channel of a transistor to operate as a ferroelectric gate. For voltages at which disturb voltages are likely to occur, the thin film varistor has a resistance obeying a formula R d >10×1/(2πfC F ), where R d is resistivity of the thin film varistor, f is an operating frequency of said memory, and C F is the capacitance of the ferroelectric layer. For voltages at or near the read and write voltage of the memory, the thin film varistor has a resistance obeying a formula R d <0.1×1/(2πfC F ).
Inventors
- 👤 Shinichiro Hayashi
- 👤 Tatsuo Otsuki
- 👤 Carlos A. Paz de Araujo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:01
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0415; G; G11; G11C; G11C11/00; G11C11/21; G11C11/22; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/689
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
41 words
An integrated circuit memory comprising: a ferroelectric field effect transistor including a ferroelectric element; a conductor for applying a voltage to said ferroelectric element; and a disturb protect device between said conductor and said ferroelectric element in said field effect transistor.
Claim 2
Dependent Claim
41 words
An integrated circuit memory comprising: a ferroelectric field effect transistor including a ferroelectric element; a conductor for applying a voltage to said ferroelectric element; and a disturb protect device between said conductor and said ferroelectric element in said field effect transistor.
Claim 3
Dependent Claim
33 words
An integrated circuit memory as in claim 1 wherein said disturb protect device comprises an electrical element selected from the group consisting of: a thin film varistor, a diode, and a Schottky diode.
Claim 4
Dependent Claim
18 words
An integrated circuit memory as in claim 1 wherein said disturb protect device comprises a thin film varistor.
Claim 5
Dependent Claim
38 words
An integrated circuit memory as in claim 1 wherein said disturb protect device has a capacitance less than one one-hundredth of a capacitance of said ferroelectric field effect transistor at operable frequencies in the intended environment of use.
Claim 6
Dependent Claim
58 words
An integrated circuit memory as in claim 1 wherein, for voltages at which disturb voltages are likely to occur, said disturb protect device has a resistance obeying a formula R.sub.d >100×1/(2πfC.sub.F), wherein R d is resistivity of said disturb protect device, f is an operating frequency of said memory, and C F is capacitance of said ferroelectric element.
Claim 7
Dependent Claim
58 words
An integrated circuit memory as in claim 1 wherein, for voltages at which disturb voltages are likely to occur, said disturb protect device has a resistance obeying a formula R.sub.d >10×1/(2πfC.sub.F), wherein R d is resistivity of said disturb protect device, f is an operating frequency of said memory, and C F is capacitance of said ferroelectric element.
Claim 8
Dependent Claim
61 words
An integrated circuit memory as in claim 1 wherein, for voltages at or near the read and write voltage of said memory, said disturb protect device has a resistance obeying a formula R.sub.d <0.01×1/(2πfC.sub.F), wherein R d is resistivity of said disturb protect device, f is an operating frequency of said memory, and C F is capacitance of said ferroelectric element.
Claim 9
Dependent Claim
61 words
An integrated circuit memory as in claim 1 wherein, for voltages at or near the read and write voltage of said memory, said disturb protect device has a resistance obeying a formula R.sub.d <0.1×1/(2πfC.sub.F), wherein R d is resistivity of said disturb protect device, f is an operating frequency of said memory, and C F is capacitance of said ferroelectric element.
Claim 10
Dependent Claim
42 words
An integrated circuit memory as in claim 1 wherein, for voltages at or near the read and write voltage of said memory, said disturb protect device has a resistance of less than 100 kiloohms and a capacitance of greater than 0.01 microfarads.
Claim 11
Dependent Claim
39 words
An integrated circuit memory as in claim 1 wherein, for voltages at which disturb voltages are likely to occur, said disturb protect device has a resistance of more than 1,600 megaohms and a capacitance of less than 1.0 picofarads.
Claim 12
Dependent Claim
42 words
An integrated circuit memory as in claim 1 wherein, for voltages at or near the read and write voltage of said memory, said disturb protect device has a resistance of less than 1000 kiloohms and a capacitance of greater than 0.001 microfarads.
Claim 13
Dependent Claim
39 words
An integrated circuit memory as in claim 1 wherein, for voltages at which disturb voltages are likely to occur, said disturb protect device has a resistance of more than 160 megaohms and a capacitance of less than 10.0 picofarads.
Claim 14
Dependent Claim
16 words
An integrated circuit memory as in claim 1 wherein said disturb protect device comprises zinc oxide.
Claim 15
Dependent Claim
40 words
An integrated circuit memory as in claim 13 wherein said zinc oxide is doped with an element selected from the group consisting of bismuth, yttrium, praseodymium, cobalt, antimony, manganese, silicon, chromium, titanium, potassium, dysprosium, cesium, cerium, iron, and mixtures thereof.
Claim 16
Dependent Claim
17 words
An integrated circuit memory as in claim 1 wherein said ferroelectric element includes a layered superlattice material.
Claim 17
Dependent Claim
37 words
An integrated circuit memory as in claim 1 wherein said disturb protect device has a capacitance less than one one-hundredth of the capacitance of said ferroelectric device at voltages at which disturb voltages are likely to occur.
Claim 18
Dependent Claim
57 words
An integrated circuit memory as in claim 1 wherein said ferroelectric field effect transistor further comprises: a substrate; a source region formed within said substrate; a drain region formed within said substrate; a channel region between said source region and said drain region; and said ferroelectric element comprises a ferroelectric gate located directly above said channel region.
Claim 19
Dependent Claim
29 words
An integrated circuit memory in claim 17 wherein said conductor comprises a first electrode and further including a second electrode between said disturb protect device and said ferroelectric gate.
Claim 20
Independent Claim
116 words
A method of operating an integrated circuit memory comprising a thin film varistor and a thin film ferroelectric field effect transistor capable of switching between a first polarization state and a second polarization state, said method comprising the steps of: delivering a first voltage pulse to said thin film varistor essentially without disturbing the polarization state of said ferroelectric field effect transistor, said first voltage pulse being of a voltage sufficient to disturb said polarization state if applied directly to said ferroelectric field effect transistor; and delivering a second voltage pulse of a higher voltage than said first voltage pulse to said thin film varistor to switch said polarization state of said ferroelectric field effect transistor.
Claim 21
Independent Claim
116 words
A method of operating an integrated circuit memory comprising a thin film varistor and a thin film ferroelectric field effect transistor capable of switching between a first polarization state and a second polarization state, said method comprising the steps of: delivering a first voltage pulse to said thin film varistor essentially without disturbing the polarization state of said ferroelectric field effect transistor, said first voltage pulse being of a voltage sufficient to disturb said polarization state if applied directly to said ferroelectric field effect transistor; and delivering a second voltage pulse of a higher voltage than said first voltage pulse to said thin film varistor to switch said polarization state of said ferroelectric field effect transistor.
Claim 22
Dependent Claim
36 words
A method as in claim 19 wherein said step of delivering a first voltage pulse without disturbing the polarization state of the ferroelectric device comprises screening said ferroelectric field effect transistor from said first voltage pulse.
References Cited (Backward Citations)
US4712876A
Cited
US5224069A
Cited
US5579258A
Cited
US5699035A
Cited
US5341325A
Cited
US5512773A
Cited
EP0702372A2
Cited
JPH08180671A
Cited
EP0847059A2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-21 | 2004-05-22 | 2004-11-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-21 | 2008-05-22 | 2008-11-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-21 | 2012-05-22 | 2012-11-21 | $7700.00 | Window Closed / Lapsed |