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US5224069A Expired / Lapsed US ⏱️ 0.0 years remaining

Ferroelectric capacitor memory circuit MOS setting and transmission transistors

Assignee: Toshiba Corp
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Filing: 1992-02-07
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Granted: 1993-06-29
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Expires: 2012-02-07
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Abstract

Abstract A is a memory circuit including a plurality of ferroelectric capacitors arranged in a matrix, setting MOS field effect transistors for setting both electrodes of each of the ferroelectric capacitor at the same electric potential, and transmission MOS field effect transistors for transmitting information to the ferroelectric capacitors, and having a construction in which two word lines are provided corresponding to each line of the ferroelectric capacitors, one bit line is provided corresponding to each row of the ferroelectric capacitors, each of the transmission MOS field effect transistors is connected to one of the word lines and the bit line, and each of the setting MOS field effect transistors is connected to the other word line. Also disclosed is a memory circuit including memory cells each composed of each of ferroelectric capacitors arranged in a matrix and transmission MOS field effect transistors provided corresponding to the ferroelectric capacitors for transmitting information to the ferroelectric capacitors, line address decoders each provided corresponding to each group of the memory cells in each line for controlling the input and output of information to the ferroelectric capacitors, word lines provided corresponding to each group of memory cells in each line for selecting the line, and drive lines for commonly controlling the ferroelectric capacitors in the group of memory cells, and having a construction in which the word lines and the drive lines are connected to the line address decoders, and bit lines are provided corresponding to each row of the memory cells.

Inventors

  • 👤 Kenji Natori

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 02:46
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/22

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 387 words
A memory circuit with ferroelectric capacitors, comprising: a plurality of storage means arranged in rows and columns forming a matrix, each storage means having one ferroelectric capacitor of a two electrode type, for storing data to be stored as a polarization state of said ferroelectric capacitor; transmission means, provided for each said storage means, for transmitting said data to said storage means and for reading said data into said storage means, said transmission means having a drain connected to one electrode of said ferroelectric capacitor; a word line, provided in each row of said rows of said plurality of said storage means, for controlling said transmission means in each said row, said word line being connected to a gate of each said transmission means in said storage means of each said row; a drive line, provided in each said row of said plurality of said storage means, for controlling said ferroelectric capacitors in each said row, said drive line being connected to another electrode of said ferroelectric capacitor in each said storage means of each said row; control means for controlling input and output operations of said ferroelectric capacitor in each said row of said plurality of said storage means by addressing said word line and said drive line, said control means being connected to said word line and said drive line in each said row; a bit line, provided in each column of said columns of said plurality of said storage means, for transmitting said data into and from said ferroelectric capacitor in each said column through said transmission means, said bit line being connected to a source of said transmission means in each said column; and sense means for reading data from or writing data into said storage means through said bit line; wherein said control means outputs a high level pulse to control said transmission means in each said row through said word line so that said storage means connected to said transmission means are commonly controlled, said sense means carries out a sense operation while said word line is at a high level and said drive line is at a low level, said sense means rereads data from or rewrites data into said storage means while said word line is at said high level and said drive line is at a high level.
Claim 2
Dependent Claim 387 words
A memory circuit with ferroelectric capacitors, comprising: a plurality of storage means arranged in rows and columns forming a matrix, each storage means having one ferroelectric capacitor of a two electrode type, for storing data to be stored as a polarization state of said ferroelectric capacitor; transmission means, provided for each said storage means, for transmitting said data to said storage means and for reading said data into said storage means, said transmission means having a drain connected to one electrode of said ferroelectric capacitor; a word line, provided in each row of said rows of said plurality of said storage means, for controlling said transmission means in each said row, said word line being connected to a gate of each said transmission means in said storage means of each said row; a drive line, provided in each said row of said plurality of said storage means, for controlling said ferroelectric capacitors in each said row, said drive line being connected to another electrode of said ferroelectric capacitor in each said storage means of each said row; control means for controlling input and output operations of said ferroelectric capacitor in each said row of said plurality of said storage means by addressing said word line and said drive line, said control means being connected to said word line and said drive line in each said row; a bit line, provided in each column of said columns of said plurality of said storage means, for transmitting said data into and from said ferroelectric capacitor in each said column through said transmission means, said bit line being connected to a source of said transmission means in each said column; and sense means for reading data from or writing data into said storage means through said bit line; wherein said control means outputs a high level pulse to control said transmission means in each said row through said word line so that said storage means connected to said transmission means are commonly controlled, said sense means carries out a sense operation while said word line is at a high level and said drive line is at a low level, said sense means rereads data from or rewrites data into said storage means while said word line is at said high level and said drive line is at a high level.
Claim 3
Dependent Claim 20 words
A memory circuit according to claim 1, wherein each said transmission means is composed of a MOS field effect transistor.
Claim 4
Dependent Claim 21 words
A memory circuit according to claim 1, wherein each said ferroelectric capacitor of said storage means is formed with lead zircon-titanate.

References Cited (Backward Citations)

US3401377A Cited
US4873664A Cited
US5038323A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-06-28 1996-12-28 1997-06-29 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-06-28 2000-12-28 2001-06-29 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-06-28 2004-12-28 2005-06-29 $7700.00 Window Closed / Lapsed

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