US7068544B2
Expired / Lapsed
US
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Flash memory with low tunnel barrier interpoly insulators
Assignee: Micron Technology Inc
•
Filing: 2001-08-30
•
Granted: 2006-06-27
•
Expires: 2021-08-30
Abstract
Abstract Structures and methods for Flash memory with low tunnel barrier intergate insulators are provided. The non-volatile memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , and Nb 2 O 5 . The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
Inventors
- 👤 Leonard Forbes
- 👤 Jerome M. Eldridge
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 00:43
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/20; H10B41/23; H10B41/27; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683; H10D30/684; H10D30/6891; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/681
Claims Analysis
Total Claims: 53
Claim 1
Independent Claim
80 words
A floating gate transistor, comprising: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator, and wherein the low tunnel barrier intergate insulator is separated from the control gate by a first metal layer.
Claim 2
Dependent Claim
80 words
A floating gate transistor, comprising: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator, and wherein the low tunnel barrier intergate insulator is separated from the control gate by a first metal layer.
Claim 3
Dependent Claim
37 words
The floating gate transistor of claim 1 , wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of lead oxide (PbO) and aluminum oxide (Al 2 O 3 ).
Claim 4
Dependent Claim
20 words
The floating gate transistor of claim 1 , wherein the low tunnel barrier intergate insulator includes a transition metal oxide.
Claim 5
Dependent Claim
37 words
The floating gate transistor of claim 3 , wherein the transition metal oxide is selected from the group consisting of Ta 2 O 5 , TiO 2 , ZrO 2 , and Nb 2 O 5 .
Claim 6
Dependent Claim
21 words
The floating gate transistor of claim 1 , wherein the low tunnel barrier intergate insulator includes a Perovskite oxide tunnel barrier.
Claim 7
Dependent Claim
33 words
The floating gate transistor of claim 1 , wherein the floating gate includes a polysilicon floating gate having a second metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
Claim 8
Dependent Claim
34 words
The floating gate transistor of claim 6 , wherein the control gate includes a polysilicon control gate having the first metal layer formed thereon in direct contact with the low tunnel barrier intergate insulator.
Claim 9
Dependent Claim
20 words
The floating gate transistor of claim 1 , wherein the floating gate transistor includes an n-channel type floating gate transistor.
Claim 10
Dependent Claim
93 words
A vertical non volatile memory cell, comprising: a first source/drain region formed on a substrate; a body region including a channel region formed on the first source/drain region; a second source/drain region formed on the body region; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator, the low tunnel barrier intergate insulator being separated from the control gate by a first metal layer.
Claim 11
Dependent Claim
93 words
A vertical non volatile memory cell, comprising: a first source/drain region formed on a substrate; a body region including a channel region formed on the first source/drain region; a second source/drain region formed on the body region; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator, the low tunnel barrier intergate insulator being separated from the control gate by a first metal layer.
Claim 12
Dependent Claim
51 words
The vertical non volatile memory cell of claim 9 , wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , and Nb 2 O 5 .
Claim 13
Dependent Claim
35 words
The vertical non volatile memory cell of claim 9 , wherein the floating gate includes a polysilicon floating gate having a second metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
Claim 14
Dependent Claim
36 words
The vertical non volatile memory cell of claim 11 , wherein the control gate includes a polysilicon control gate having the first metal layer formed thereon in direct contact with the low tunnel barrier intergate insulator.
Claim 15
Dependent Claim
25 words
The vertical non volatile memory cell of claim 9 , wherein the floating gate includes a vertical floating gate formed alongside of the body region.
Claim 16
Dependent Claim
26 words
The vertical non volatile memory cell of claim 13 , wherein the control gate includes a vertical control gate formed alongside of the vertical floating gate.
Claim 17
Dependent Claim
26 words
The vertical non volatile memory cell of claim 9 , wherein the floating gate includes a horizontally oriented floating gate formed alongside of the body region.
Claim 18
Dependent Claim
27 words
The vertical non volatile memory cell of claim 15 , wherein the control gate includes a horizontally oriented control gate formed above the horizontally oriented floating gate.
Claim 19
Dependent Claim
80 words
A non-volatile memory cell, comprising: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a polysilicon floating gate opposing the channel region and separated therefrom by a gate oxide; a first metal layer formed on the polysilicon floating gate; a metal oxide intergate insulator formed on the first metal layer; a second metal layer formed on the metal oxide intergate insulator; and a polysilicon control gate formed on the second metal layer.
Claim 20
Dependent Claim
80 words
A non-volatile memory cell, comprising: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a polysilicon floating gate opposing the channel region and separated therefrom by a gate oxide; a first metal layer formed on the polysilicon floating gate; a metal oxide intergate insulator formed on the first metal layer; a second metal layer formed on the metal oxide intergate insulator; and a polysilicon control gate formed on the second metal layer.
Claim 21
Dependent Claim
27 words
The non-volatile memory cell of claim 17 , wherein first and the second metal layers are lead and the metal oxide intergate insulator is lead oxide (PbO).
Claim 22
Dependent Claim
31 words
The non-volatile memory cell of claim 17 , wherein the first and second metal layers are aluminum and the metal oxide intergate insulator is aluminum oxide (Al 2 O 3 ).
Claim 23
Dependent Claim
33 words
The non-volatile memory cell of claim 17 , wherein the first and the second metal layers include transition metal layers and the metal oxide intergate insulator includes a transition metal oxide intergate insulator.
Claim 24
Dependent Claim
37 words
The non-volatile memory cell of claim 20 , wherein the transition metal oxide is selected from the group consisting of Ta 2 O 5 , TiO 2 , ZrO 2 , and Nb 2 O 5 .
Claim 25
Dependent Claim
20 words
The non-volatile memory cell of claim 20 , wherein the metal oxide intergate insulator includes a Perovskite oxide intergate insulator.
Claim 26
Dependent Claim
19 words
The non-volatile memory cell of claim 17 , wherein the floating gate transistor includes a vertical floating gate transistor.
Claim 27
Dependent Claim
25 words
The floating gate transistor of claim 1 , wherein the low tunnel barrier integrate insulator includes a metal oxide insulator consisting of lead oxide (PbO).
Claim 28
Dependent Claim
19 words
The floating gate transistor of claim 3 , wherein the transition metal oxide is Ta 2 O 5 .
Claim 29
Dependent Claim
17 words
The floating gate transistor of claim 3 , wherein the transition metal oxide is TiO 2 .
Claim 30
Dependent Claim
19 words
The floating gate transistor of claim 3 , wherein the transition metal oxide is Nb 2 O 5 .
Claim 31
Dependent Claim
34 words
The floating gate transistor of claim 7 , wherein the insulator is a metal oxide insulator layer and the metal layers include the same metal material used to form the metal oxide insulator layer.
Claim 32
Dependent Claim
36 words
The vertical non volatile memory cell of claim 12 , wherein the insulator is a metal oxide insulator layer and the metal layers include the same metal material used to form the metal oxide insulator layer.
Claim 33
Dependent Claim
28 words
The non-volatile memory cell of claim 17 , wherein the first and second metal layers include the same metal material used to form the metal oxide insulator layer.
Claim 34
Dependent Claim
73 words
A floating gate transistor, comprising: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator, the low tunnel barrier intergate insulator including a Perovskite oxide tunnel barrier.
Claim 35
Dependent Claim
73 words
A floating gate transistor, comprising: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator, the low tunnel barrier intergate insulator including a Perovskite oxide tunnel barrier.
Claim 36
Dependent Claim
84 words
A floating gate transistor, comprising: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator, the control gate including a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
Claim 37
Dependent Claim
84 words
A floating gate transistor, comprising: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator, the control gate including a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
Claim 38
Dependent Claim
100 words
A vertical non volatile memory cell, comprising: a first source/drain region formed on a substrate; a body region including a channel region formed on the first source/drain region; a second source/drain region formed on the body region; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator, the control gate including a polysilicon control gate having a first metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
Claim 39
Dependent Claim
100 words
A vertical non volatile memory cell, comprising: a first source/drain region formed on a substrate; a body region including a channel region formed on the first source/drain region; a second source/drain region formed on the body region; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator, the control gate including a polysilicon control gate having a first metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
Claim 40
Dependent Claim
24 words
The vertical non volatile memory cell of claim 33 , wherein the low tunnel barrier intergate insulator includes a metal oxide insulator comprising PbO.
Claim 41
Dependent Claim
28 words
The vertical non volatile memory cell of claim 33 , wherein the low tunnel barrier intergate insulator includes a metal oxide insulator comprising Ta 2 O 5 .
Claim 42
Dependent Claim
26 words
The vertical non volatile memory cell of claim 33 , wherein the low tunnel barrier intergate insulator includes a metal oxide insulator comprising TiO 2 .
Claim 43
Dependent Claim
28 words
The vertical non volatile memory cell of claim 33 , wherein the low tunnel barrier intergate insulator includes a metal oxide insulator comprising Nb 2 O 5 .
Claim 44
Dependent Claim
91 words
A vertical non volatile memory cell, comprising: a first source/drain region formed on a substrate; a body region including a channel region formed on the first source/drain region; a second source/drain region formed on the body region; a floating gate opposing the channel region and separated therefrom by a gate oxide, the floating gate including a horizontally oriented floating gate formed alongside of the body region; a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator.
Claim 45
Dependent Claim
91 words
A vertical non volatile memory cell, comprising: a first source/drain region formed on a substrate; a body region including a channel region formed on the first source/drain region; a second source/drain region formed on the body region; a floating gate opposing the channel region and separated therefrom by a gate oxide, the floating gate including a horizontally oriented floating gate formed alongside of the body region; a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator.
Claim 46
Dependent Claim
27 words
The vertical non volatile memory cell of claim 38 , wherein the control gate includes a horizontally oriented control gate formed above the horizontally oriented floating gate.
Claim 47
Dependent Claim
100 words
A non-volatile memory cell, comprising: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a polysilicon floating gate opposing the channel region and separated therefrom by a gate oxide; a first metal layer formed on the polysilicon floating gate; a metal oxide intergate insulator formed on the first metal layer; a second metal layer formed on the metal oxide intergate insulator, wherein the first and the second metal layers are lead and the metal oxide intergate insulator is lead oxide (PbO); and a polysilicon control gate formed on the second metal layer.
Claim 48
Dependent Claim
100 words
A non-volatile memory cell, comprising: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a polysilicon floating gate opposing the channel region and separated therefrom by a gate oxide; a first metal layer formed on the polysilicon floating gate; a metal oxide intergate insulator formed on the first metal layer; a second metal layer formed on the metal oxide intergate insulator, wherein the first and the second metal layers are lead and the metal oxide intergate insulator is lead oxide (PbO); and a polysilicon control gate formed on the second metal layer.
Claim 49
Dependent Claim
104 words
A non-volatile memory cell, comprising: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a polysilicon floating gate opposing the channel region and separated therefrom by a gate oxide; a first metal layer formed on the polysilicon floating gate; a metal oxide intergate insulator formed on the first metal layer; a second metal layer formed on the metal oxide intergate insulator, the first and the second metal layers include transition metal layers and the metal oxide intergate insulator includes a transition metal oxide intergate insulator; and a polysilicon control gate formed on the second metal layer.
Claim 50
Dependent Claim
104 words
A non-volatile memory cell, comprising: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a polysilicon floating gate opposing the channel region and separated therefrom by a gate oxide; a first metal layer formed on the polysilicon floating gate; a metal oxide intergate insulator formed on the first metal layer; a second metal layer formed on the metal oxide intergate insulator, the first and the second metal layers include transition metal layers and the metal oxide intergate insulator includes a transition metal oxide intergate insulator; and a polysilicon control gate formed on the second metal layer.
Claim 51
Dependent Claim
37 words
The non-volatile memory cell of claim 41 , wherein the transition metal oxide is selected from the group consisting of Ta 2 O 5 , TiO 2 , ZrO 2 , and Nb 2 O 5 .
Claim 52
Dependent Claim
91 words
A non-volatile memory cell, comprising: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a polysilicon floating gate opposing the channel region and separated therefrom by a gate oxide; a first metal layer formed on the polysilicon floating gate; a metal oxide intergate insulator formed on the first metal layer, the metal oxide intergate insulator includes a Perovskite oxide intergate insulator; a second metal layer formed on the metal oxide intergate insulator; and a polysilicon control gate fanned on the second metal layer.
Claim 53
Dependent Claim
91 words
A non-volatile memory cell, comprising: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a polysilicon floating gate opposing the channel region and separated therefrom by a gate oxide; a first metal layer formed on the polysilicon floating gate; a metal oxide intergate insulator formed on the first metal layer, the metal oxide intergate insulator includes a Perovskite oxide intergate insulator; a second metal layer formed on the metal oxide intergate insulator; and a polysilicon control gate fanned on the second metal layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2009-06-26 | 2009-12-26 | 2010-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2013-06-26 | 2013-12-26 | 2014-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2017-06-26 | 2017-12-26 | 2018-06-27 | $7700.00 | Window Closed / Lapsed |