Low resistance gate flash memory

Claim 2

A floating gate stack, comprising: a first polysilicon layer; a dielectric layer over the first polysilicon layer; a second polysilicon layer over the dielectric layer; a barrier layer over the second polysilicon layer; a metal layer over the barrier layer; a cap layer over the metal layer; an oxidation barrier adjacent sidewalls of at least the metal layer; and a sidewall oxide layer adjacent sidewalls of at least the first poysilicon layer.

Claim 3

The floating gate stack of claim 1 , wherein at least one of the first polysilicon layer and the second polysilicon layer are conductively doped.

Claim 4

The floating gate stack of claim 1 , wherein the dielectric layer comprises a dielectric material selected from the group consisting of ONO, tantalum oxide, barium strontium titanate and silicon nitride.

Claim 5

The floating gate stack of claim 1 , wherein the barrier layer comprises a metal nitride selected from the group consisting of tungsten nitride and titanium nitride.

Claim 6

The floating gate stack of claim 1 , wherein the metal layer comprises a refractory metal selected from the group consisting of titanium, tungsten, tantalum, cobalt and molybdenum.

Claim 7

The floating gate stack of claim 1 , wherein the metal layer comprises tungsten.

Claim 8

The floating gate stack of claim 1 , wherein the cap layer comprises silicon nitride.

Claim 9

The floating gate stack of claim 1 , wherein the oxidation barrier comprises silicon nitride.

Claim 10

The floating gate stack of claim 1 , further comprising a spacer layer comprising an insulator material selected from the group consisting of silicon oxides, silicon nitrides and silicon oxynitrides, and adjacent the oxidation barrier and the sidewall oxide layer.

Claim 11

A floating gate stack, comprising: a first polysilicon layer; a dielectric layer over the first polysilicon layer comprising a dielectric material selected from the group consisting of ONO, tantalum oxide, barium strontium titanate and silicon nitride; a second polysilicon layer over the dielectric layer; a barrier layer over the second polysilicon layer comprising a metal nitride; a metal layer over the barrier layer comprising a refractory metal selected from the group consisting of titanium, tungsten, tantalum, cobalt and molybdenum; a nitride layer over the metal layer; an oxidation barrier comprising nitride adjacent sidewalls of at least the metal layer; a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer; and a spacer layer comprising an insulator material selected from the group consisting of silicon oxides, silicon nitrides and silicon oxynitrides, and adjacent the oxidation barrier and the sidewall oxide layer.

Claim 12

A floating gate stack, comprising: a first polysilicon layer; a dielectric layer over the first polysilicon layer comprising a dielectric material selected from the group consisting of ONO, tantalum oxide, barium strontium titanate and silicon nitride; a second polysilicon layer over the dielectric layer; a barrier layer over the second polysilicon layer comprising a metal nitride; a metal layer over the barrier layer comprising a refractory metal selected from the group consisting of titanium, tungsten, tantalum, cobalt and molybdenum; a nitride layer over the metal layer; an oxidation barrier comprising nitride adjacent sidewalls of at least the metal layer; a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer; and a spacer layer comprising an insulator material selected from the group consisting of silicon oxides, silicon nitrides and silicon oxynitrides, and adjacent the oxidation barrier and the sidewall oxide layer.

Claim 13

A floating gate stack, comprising: a first polysilicon layer; a dielectric layer over the first polysilicon layer comprising an ONO dielectric; a second polysilicon layer over the dielectric layer; a barrier layer over the second polysilicon layer comprising a metal nitride selected from the group consisting of tungsten nitride and titanium nitride; a tungsten layer over the barrier layer; a first nitride layer over the tungsten layer; a second nitride layer adjacent sidewalls of at least the tungsten layer; a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer; and a spacer layer comprising an insulator material selected from the group consisting of silicon oxides, silicon nitrides and silicon oxynitrides, and adjacent the oxidation barrier and the sidewall oxide layer.

Claim 14

A floating gate stack, comprising: a first polysilicon layer; a dielectric layer over the first polysilicon layer comprising an ONO dielectric; a second polysilicon layer over the dielectric layer; a barrier layer over the second polysilicon layer comprising a metal nitride selected from the group consisting of tungsten nitride and titanium nitride; a tungsten layer over the barrier layer; a first nitride layer over the tungsten layer; a second nitride layer adjacent sidewalls of at least the tungsten layer; a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer; and a spacer layer comprising an insulator material selected from the group consisting of silicon oxides, silicon nitrides and silicon oxynitrides, and adjacent the oxidation barrier and the sidewall oxide layer.

Claim 15

A floating gate stack, comprising: a first polysilicon layer; a second polysilicon layer; a dielectric layer interposed between the first polysilicon layer and the second polysilicon layer; a metal layer; a barrier layer interposed between the metal layer and the second polysilicon layer; a cap layer over the metal layer; an oxidation barrier adjacent sidewalls of at least the metal layer; and a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer.

Claim 16

A floating gate stack, comprising: a first polysilicon layer; a second polysilicon layer; a dielectric layer interposed between the first polysilicon layer and the second polysilicon layer; a metal layer; a barrier layer interposed between the metal layer and the second polysilicon layer; a cap layer over the metal layer; an oxidation barrier adjacent sidewalls of at least the metal layer; and a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer.

Claim 17

The floating gate stack of claim 12 , wherein at least one of the first polysilicon layer and the second polysilicon layer are conductively doped.

Claim 18

The floating gate stack of claim 12 , wherein the dielectric layer comprises a dielectric material selected from the group consisting of ONO, tantalum oxide, barium strontium titanate and silicon nitride.

Claim 19

The floating gate stack of claim 12 , wherein the barrier layer comprises a metal nitride selected from the group consisting of tungsten nitride and titanium nitride.

Claim 20

The floating gate stack of claim 12 , wherein the metal layer comprises a refractory metal selected from the group consisting of titanium, tungsten, tantalum, cobalt and molybdenum.

Claim 21

The floating gate stack of claim 12 , wherein the metal layer comprises tungsten.

Claim 22

The floating gate stack of claim 12 , wherein the cap layer comprises silicon nitride.

Claim 23

The floating gate stack of claim 12 , wherein the oxidation barrier comprises silicon nitride.

Claim 24

The floating gate stack of claim 12 , further comprising a spacer layer comprising an insulator material selected from the group consisting of silicon oxides, silicon nitrides and silicon oxynitrides, and adjacent the oxidation barrier and the sidewall oxide layer.

Claim 25

A floating gate stack, comprising: a first polysilicon layer; a second polysilicon layer; a dielectric layer comprising a dielectric material selected from the group consisting of ONO, tantalum oxide, barium strontium titanate and silicon nitride, and interposed between the first polysilicon layer and the second polysilicon layer; a metal layer comprising a refractory metal selected from the group consisting of titanium, tungsten, tantalum, cobalt and molybdenum; a barrier layer comprising a metal nitride and interposed between the metal layer and the second polysilicon layer; a nitride layer over the metal layer; an oxidation barrier comprising nitride adjacent sidewalls of at least the metal layer; a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer; and a spacer layer comprising an insulator material selected from the group consisting of silicon oxides, silicon nitrides and silicon oxynitrides, and adjacent the oxidation barrier and the sidewall oxide layer.

Claim 26

A floating gate stack, comprising: a first polysilicon layer; a second polysilicon layer; a dielectric layer comprising a dielectric material selected from the group consisting of ONO, tantalum oxide, barium strontium titanate and silicon nitride, and interposed between the first polysilicon layer and the second polysilicon layer; a metal layer comprising a refractory metal selected from the group consisting of titanium, tungsten, tantalum, cobalt and molybdenum; a barrier layer comprising a metal nitride and interposed between the metal layer and the second polysilicon layer; a nitride layer over the metal layer; an oxidation barrier comprising nitride adjacent sidewalls of at least the metal layer; a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer; and a spacer layer comprising an insulator material selected from the group consisting of silicon oxides, silicon nitrides and silicon oxynitrides, and adjacent the oxidation barrier and the sidewall oxide layer.

Claim 27

A floating gate stack, comprising: a first polysilicon layer; a second polysilicon layer; a dielectric layer comprising an ONO dielectric and interposed between the first polysilicon layer and the second polysilicon layer; a tungsten layer; a metal nitride layer comprising a metal nitride selected from the group consisting of tungsten nitride and titanium nitride, and interposed between the tungsten layer and the second polysilicon layer; a first nitride layer over the tungsten layer; a second nitride layer adjacent sidewalls of at least the tungsten layer; a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer; and a spacer layer comprising an insulator material selected from the group consisting of silicon oxides, silicon nitrides and silicon oxynitrides, and adjacent the second nitride layer and the sidewall oxide layer.

Claim 28

A floating gate stack, comprising: a first polysilicon layer; a second polysilicon layer; a dielectric layer comprising an ONO dielectric and interposed between the first polysilicon layer and the second polysilicon layer; a tungsten layer; a metal nitride layer comprising a metal nitride selected from the group consisting of tungsten nitride and titanium nitride, and interposed between the tungsten layer and the second polysilicon layer; a first nitride layer over the tungsten layer; a second nitride layer adjacent sidewalls of at least the tungsten layer; a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer; and a spacer layer comprising an insulator material selected from the group consisting of silicon oxides, silicon nitrides and silicon oxynitrides, and adjacent the second nitride layer and the sidewall oxide layer.

Claim 29

A semiconductor die, comprising: a substrate; and an integrated circuit supported by the substrate and having at least one floating gate stack, the at least one floating gate stack comprising: a first polysilicon layer; a dielectric layer over the first polysilicon layer; a second polysilicon layer over the dielectric layer; a barrier layer over the second polysilicon layer; a metal layer over the barrier layer; a cap layer over the metal layer; an oxidation barrier adjacent sidewalls of at least the metal layer; and a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer.

Claim 30

A semiconductor die, comprising: a substrate; and an integrated circuit supported by the substrate and having at least one floating gate stack, the at least one floating gate stack comprising: a first polysilicon layer; a dielectric layer over the first polysilicon layer; a second polysilicon layer over the dielectric layer; a barrier layer over the second polysilicon layer; a metal layer over the barrier layer; a cap layer over the metal layer; an oxidation barrier adjacent sidewalls of at least the metal layer; and a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer.

Claim 31

The semiconductor die of claim 23 , wherein the metal layer comprises a refractory metal selected from the group consisting of titanium, tungsten, tantalum, cobalt and molybdenum.

Claim 32

The semiconductor die of claim 23 , wherein the metal layer comprises tungsten.

Claim 33

The semiconductor die of claim 23 , wherein the at least one floating gate stack further comprises a spacer layer comprising an insulator material selected from the group consisting of silicon oxides, silicon nitrides and silicon oxynitrides, and adjacent the oxidation barrier and the sidewall oxide layer.

Claim 34

A semiconductor die, comprising: a substrate; and an integrated circuit supported by the substrate and having at least one floating gate stack, the at least one floating gate stack comprising: a first polysilicon layer; a dielectric layer over the first polysilicon layer comprising a dielectric material selected from the group consisting of ONO, tantalum oxide, barium strontium titanate and silicon nitride; a second polysilicon layer over the dielectric layer; a barrier layer over the second polysilicon layer comprising a metal nitride; a metal layer over the barrier layer comprising a refractory metal selected from the group consisting of titanium, tungsten, tantalum, cobalt and molybdenum; a nitride layer over the metal layer; an oxidation barrier comprising nitride adjacent sidewalls of at least the metal layer; a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer; and a spacer layer comprising an insulator material selected from the group consisting of silicon oxides, silicon nitrides and silicon oxynitrides, and adjacent the oxidation barrier and the sidewall oxide layer.

Claim 35

A semiconductor die, comprising: a substrate; and an integrated circuit supported by the substrate and having at least one floating gate stack, the at least one floating gate stack comprising: a first polysilicon layer; a dielectric layer over the first polysilicon layer comprising a dielectric material selected from the group consisting of ONO, tantalum oxide, barium strontium titanate and silicon nitride; a second polysilicon layer over the dielectric layer; a barrier layer over the second polysilicon layer comprising a metal nitride; a metal layer over the barrier layer comprising a refractory metal selected from the group consisting of titanium, tungsten, tantalum, cobalt and molybdenum; a nitride layer over the metal layer; an oxidation barrier comprising nitride adjacent sidewalls of at least the metal layer; a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer; and a spacer layer comprising an insulator material selected from the group consisting of silicon oxides, silicon nitrides and silicon oxynitrides, and adjacent the oxidation barrier and the sidewall oxide layer.

Claim 36

A semiconductor die, comprising: a substrate; and an integrated circuit supported by the substrate and having at least one floating gate stack, the at least one floating gate stack comprising: a first polysilicon layer; a second polysilicon layer; a dielectric layer interposed between the first polysilicon layer and the second polysilicon layer; a metal layer; a barrier layer interposed between the metal layer and the second polysilicon layer; a cap layer over the metal layer; an oxidation barrier adjacent sidewalls of at least the metal layer; and a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer.

Claim 37

A semiconductor die, comprising: a substrate; and an integrated circuit supported by the substrate and having at least one floating gate stack, the at least one floating gate stack comprising: a first polysilicon layer; a second polysilicon layer; a dielectric layer interposed between the first polysilicon layer and the second polysilicon layer; a metal layer; a barrier layer interposed between the metal layer and the second polysilicon layer; a cap layer over the metal layer; an oxidation barrier adjacent sidewalls of at least the metal layer; and a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer.

Claim 38

The semiconductor die of claim 28 , wherein the metal layer comprises a refractory metal selected from the group consisting of titanium, tungsten, tantalum, cobalt and molybdenum.

Claim 39

The semiconductor die of claim 28 , wherein the metal layer comprises tungsten.

Claim 40

The semiconductor die of claim 28 , wherein the floating gate stack further comprises a spacer layer comprising an insulator material selected from the group consisting of silicon oxides, silicon nitrides and silicon oxynitrides, and adjacent the oxidation barrier and the sidewall oxide layer.

Claim 41

A semiconductor die, comprising: a substrate; and an integrated circuit supported by the substrate and having at least one floating gate stack, the at least one floating gate stack comprising: a first polysilicon layer; a second polysilicon layer; a dielectric layer comprising a dielectric material selected from the group consisting of ONO, tantalum oxide, barium strontium titanate and silicon nitride, and interposed between the first polysilicon layer and the second polysilicon layer; a metal layer comprising a refractory metal selected from the group consisting of titanium, tungsten, tantalum, cobalt and molybdenum; a barrier layer comprising a metal nitride and interposed between the metal layer and the second polysilicon layer; a nitride layer over the metal layer; an oxidation barrier comprising nitride adjacent sidewalls of at least the metal layer; a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer; and a spacer layer comprising an insulator material selected from the group consisting of silicon oxides, silicon nitrides and silicon oxynitrides, and adjacent the oxidation barrier and the sidewall oxide layer.

Claim 42

A semiconductor die, comprising: a substrate; and an integrated circuit supported by the substrate and having at least one floating gate stack, the at least one floating gate stack comprising: a first polysilicon layer; a second polysilicon layer; a dielectric layer comprising a dielectric material selected from the group consisting of ONO, tantalum oxide, barium strontium titanate and silicon nitride, and interposed between the first polysilicon layer and the second polysilicon layer; a metal layer comprising a refractory metal selected from the group consisting of titanium, tungsten, tantalum, cobalt and molybdenum; a barrier layer comprising a metal nitride and interposed between the metal layer and the second polysilicon layer; a nitride layer over the metal layer; an oxidation barrier comprising nitride adjacent sidewalls of at least the metal layer; a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer; and a spacer layer comprising an insulator material selected from the group consisting of silicon oxides, silicon nitrides and silicon oxynitrides, and adjacent the oxidation barrier and the sidewall oxide layer.

Claim 43

A flash memory device, comprising: an array of floating gate memory cells; a row decoder circuit coupled to the array of floating gate memory cells; a column decoder circuit coupled to the array of floating gate memory cells; and an address buffer circuit coupled to the row decoder circuit and the column decoder circuit; wherein at least one of the floating gate memory cells has a floating gate stack comprising: a first polysilicon layer; a dielectric layer over the first polysilicon layer comprising a dielectric material selected from the group consisting of ONO, tantalum oxide, barium strontium titanate and silicon nitride; a second polysilicon layer over the dielectric layer; a barrier layer over the second polysilicon layer comprising a metal nitride; a metal layer over the barrier layer comprising a refractory metal selected from the group consisting of titanium, tungsten, tantalum, cobalt and molybdenum; a nitride layer over the metal layer; an oxidation barrier comprising nitride adjacent sidewalls of at least the metal layer; and a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer.

Claim 44

A flash memory device, comprising: an array of floating gate memory cells; a row decoder circuit coupled to the array of floating gate memory cells; a column decoder circuit coupled to the array of floating gate memory cells; and an address buffer circuit coupled to the row decoder circuit and the column decoder circuit; wherein at least one of the floating gate memory cells has a floating gate stack comprising: a first polysilicon layer; a dielectric layer over the first polysilicon layer comprising a dielectric material selected from the group consisting of ONO, tantalum oxide, barium strontium titanate and silicon nitride; a second polysilicon layer over the dielectric layer; a barrier layer over the second polysilicon layer comprising a metal nitride; a metal layer over the barrier layer comprising a refractory metal selected from the group consisting of titanium, tungsten, tantalum, cobalt and molybdenum; a nitride layer over the metal layer; an oxidation barrier comprising nitride adjacent sidewalls of at least the metal layer; and a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer.

Claim 45

A flash memory device, comprising: an array of floating gate memory cells; a row decoder circuit coupled to the array of floating gate memory cells; a column decoder circuit coupled to the array of floating gate memory cells; and an address buffer circuit coupled to the row decoder circuit and the column decoder circuit; wherein at least one of the floating gate memory cells has a floating gate stack comprising: a first polysilicon layer; a second polysilicon layer; a dielectric layer comprising a dielectric material selected from the group consisting of ONO, tantalum oxide, barium strontium titanate and silicon nitride, and interposed between the first polysilicon layer and the second polysilicon layer; a metal layer comprising a refractory metal selected from the group consisting of titanium, tungsten, tantalum, cobalt and molybdenum; a barrier layer comprising a metal nitride and interposed between the metal layer and the second polysilicon layer; a nitride layer over the metal layer; an oxidation barrier comprising nitride adjacent sidewalls of at least the metal layer; and a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer.

Claim 46

A flash memory device, comprising: an array of floating gate memory cells; a row decoder circuit coupled to the array of floating gate memory cells; a column decoder circuit coupled to the array of floating gate memory cells; and an address buffer circuit coupled to the row decoder circuit and the column decoder circuit; wherein at least one of the floating gate memory cells has a floating gate stack comprising: a first polysilicon layer; a second polysilicon layer; a dielectric layer comprising a dielectric material selected from the group consisting of ONO, tantalum oxide, barium strontium titanate and silicon nitride, and interposed between the first polysilicon layer and the second polysilicon layer; a metal layer comprising a refractory metal selected from the group consisting of titanium, tungsten, tantalum, cobalt and molybdenum; a barrier layer comprising a metal nitride and interposed between the metal layer and the second polysilicon layer; a nitride layer over the metal layer; an oxidation barrier comprising nitride adjacent sidewalls of at least the metal layer; and a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer.

Claim 47

A memory module, comprising: a support; a plurality of leads extending from the support; a command link coupled to at least one of the plurality of leads; a plurality of data links, wherein each data link is coupled to at least one of the plurality of leads; and at least one flash memory device contained on the support and coupled to the command link, wherein the at least one flash memory device comprises: an array of floating gate memory cells; a row decoder circuit coupled to the array of floating gate memory cells; a column decoder circuit coupled to the array of floating gate memory cells; and an address buffer circuit coupled to the row decoder circuit and the column decoder circuit; wherein at least one of the floating gate memory cells has a floating gate stack comprising: a first polysilicon layer; a dielectric layer over the first polysilicon layer comprising a dielectric material selected from the group consisting of ONO, tantalum oxide, barium strontium titanate and silicon nitride; a second polysilicon layer over the dielectric layer; a barrier layer over the second polysilicon layer comprising a metal nitride; a metal layer over the barrier layer comprising a refractory metal selected from the group consisting of titanium, tungsten, tantalum, cobalt and molybdenum; a nitride layer over the metal layer; an oxidation barrier comprising nitride adjacent sidewalls of at least the metal layer; and a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer.

Claim 48

A memory module, comprising: a support; a plurality of leads extending from the support; a command link coupled to at least one of the plurality of leads; a plurality of data links, wherein each data link is coupled to at least one of the plurality of leads; and at least one flash memory device contained on the support and coupled to the command link, wherein the at least one flash memory device comprises: an array of floating gate memory cells; a row decoder circuit coupled to the array of floating gate memory cells; a column decoder circuit coupled to the array of floating gate memory cells; and an address buffer circuit coupled to the row decoder circuit and the column decoder circuit; wherein at least one of the floating gate memory cells has a floating gate stack comprising: a first polysilicon layer; a dielectric layer over the first polysilicon layer comprising a dielectric material selected from the group consisting of ONO, tantalum oxide, barium strontium titanate and silicon nitride; a second polysilicon layer over the dielectric layer; a barrier layer over the second polysilicon layer comprising a metal nitride; a metal layer over the barrier layer comprising a refractory metal selected from the group consisting of titanium, tungsten, tantalum, cobalt and molybdenum; a nitride layer over the metal layer; an oxidation barrier comprising nitride adjacent sidewalls of at least the metal layer; and a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer.

Claim 49

A memory module, comprising: a support; a plurality of leads extending from the support; a command link coupled to at least one of the plurality of leads; a plurality of data links, wherein each data link is coupled to at least one of the plurality of leads; and at least one flash memory device contained on the support and coupled to the command link, wherein the at least one flash memory device comprises: an array of floating gate memory cells; a row decoder circuit coupled to the array of floating gate memory cells; a column decoder circuit coupled to the array of floating gate memory cells; and an address buffer circuit coupled to the row decoder circuit and the column decoder circuit; wherein at least one of the floating gate memory cells has a floating gate stack comprising: a first polysilicon layer; a second polysilicon layer; a dielectric layer comprising a dielectric material selected from the group consisting of ONO, tantalum oxide, barium strontium titanate and silicon nitride, and interposed between the first polysilicon layer and the second polysilicon layer; a metal layer comprising a refractory metal selected from the group consisting of titanium, tungsten, tantalum, cobalt and molybdenum; a barrier layer comprising a metal nitride and interposed between the metal layer and the second polysilicon layer; a nitride layer over the metal layer; an oxidation barrier comprising nitride adjacent sidewalls of at least the metal layer; and a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer.

Claim 50

A memory module, comprising: a support; a plurality of leads extending from the support; a command link coupled to at least one of the plurality of leads; a plurality of data links, wherein each data link is coupled to at least one of the plurality of leads; and at least one flash memory device contained on the support and coupled to the command link, wherein the at least one flash memory device comprises: an array of floating gate memory cells; a row decoder circuit coupled to the array of floating gate memory cells; a column decoder circuit coupled to the array of floating gate memory cells; and an address buffer circuit coupled to the row decoder circuit and the column decoder circuit; wherein at least one of the floating gate memory cells has a floating gate stack comprising: a first polysilicon layer; a second polysilicon layer; a dielectric layer comprising a dielectric material selected from the group consisting of ONO, tantalum oxide, barium strontium titanate and silicon nitride, and interposed between the first polysilicon layer and the second polysilicon layer; a metal layer comprising a refractory metal selected from the group consisting of titanium, tungsten, tantalum, cobalt and molybdenum; a barrier layer comprising a metal nitride and interposed between the metal layer and the second polysilicon layer; a nitride layer over the metal layer; an oxidation barrier comprising nitride adjacent sidewalls of at least the metal layer; and a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer.

Claim 51

A memory system, comprising: a controller; a command link coupled to the controller; a data link coupled to the controller; and a flash memory device coupled to the command link and the data link, wherein the flash memory device comprises: an array of floating gate memory cells; a row decoder circuit coupled to the array of floating gate memory cells; a column decoder circuit coupled to the array of floating gate memory cells; and an address buffer circuit coupled to the row decoder circuit and the column decoder circuit; wherein at least one of the floating gate memory cells has a floating gate stack comprising: a first polysilicon layer; a dielectric layer over the first polysilicon layer comprising a dielectric material selected from the group consisting of ONO, tantalum oxide, barium strontium titanate and silicon nitride; a second polysilicon layer over the dielectric layer; a barrier layer over the second polysilicon layer comprising a metal nitride; a metal layer over the barrier layer comprising a refractory metal selected from the group consisting of titanium, tungsten, tantalum, cobalt and molybdenum; a nitride layer over the metal layer; an oxidation barrier comprising nitride adjacent sidewalls of at least the metal layer; and a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer.

Claim 52

A memory system, comprising: a controller; a command link coupled to the controller; a data link coupled to the controller; and a flash memory device coupled to the command link and the data link, wherein the flash memory device comprises: an array of floating gate memory cells; a row decoder circuit coupled to the array of floating gate memory cells; a column decoder circuit coupled to the array of floating gate memory cells; and an address buffer circuit coupled to the row decoder circuit and the column decoder circuit; wherein at least one of the floating gate memory cells has a floating gate stack comprising: a first polysilicon layer; a dielectric layer over the first polysilicon layer comprising a dielectric material selected from the group consisting of ONO, tantalum oxide, barium strontium titanate and silicon nitride; a second polysilicon layer over the dielectric layer; a barrier layer over the second polysilicon layer comprising a metal nitride; a metal layer over the barrier layer comprising a refractory metal selected from the group consisting of titanium, tungsten, tantalum, cobalt and molybdenum; a nitride layer over the metal layer; an oxidation barrier comprising nitride adjacent sidewalls of at least the metal layer; and a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer.

Claim 53

A memory system, comprising: a controller; a command link coupled to the controller; a data link coupled to the controller; and a flash memory device coupled to the command link and the data link, wherein the flash memory device comprises: an array of floating gate memory cells; a row decoder circuit coupled to the array of floating gate memory cells; a column decoder circuit coupled to the array of floating gate memory cells; and an address buffer circuit coupled to the row decoder circuit and the column decoder circuit; wherein at least one of the floating gate memory cells has a floating gate stack comprising: a first polysilicon layer; a second polysilicon layer; a dielectric layer comprising a dielectric material selected from the group consisting of ONO, tantalum oxide, barium strontium titanate and silicon nitride, and interposed between the first polysilicon layer and the second polysilicon layer; a metal layer comprising a refractory metal selected from the group consisting of titanium, tungsten, tantalum, cobalt and molybdenum; a barrier layer comprising a metal nitride and interposed between the metal layer and the second polysilicon layer; a nitride layer over the metal layer; an oxidation barrier comprising nitride adjacent sidewalls of at least the metal layer; and a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer.

Claim 54

A memory system, comprising: a controller; a command link coupled to the controller; a data link coupled to the controller; and a flash memory device coupled to the command link and the data link, wherein the flash memory device comprises: an array of floating gate memory cells; a row decoder circuit coupled to the array of floating gate memory cells; a column decoder circuit coupled to the array of floating gate memory cells; and an address buffer circuit coupled to the row decoder circuit and the column decoder circuit; wherein at least one of the floating gate memory cells has a floating gate stack comprising: a first polysilicon layer; a second polysilicon layer; a dielectric layer comprising a dielectric material selected from the group consisting of ONO, tantalum oxide, barium strontium titanate and silicon nitride, and interposed between the first polysilicon layer and the second polysilicon layer; a metal layer comprising a refractory metal selected from the group consisting of titanium, tungsten, tantalum, cobalt and molybdenum; a barrier layer comprising a metal nitride and interposed between the metal layer and the second polysilicon layer; a nitride layer over the metal layer; an oxidation barrier comprising nitride adjacent sidewalls of at least the metal layer; and a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer.

Claim 55

An electronic system, comprising: a processor; and a circuit module having a plurality of leads coupled to the processor, and further having a semiconductor die coupled to at least a portion of the plurality of leads, wherein the semiconductor die comprises: a substrate; and an integrated circuit supported by the substrate and having at least one floating gate stack, the at least one floating gate stack comprising: a first polysilicon layer; a dielectric layer over the first polysilicon layer comprising a dielectric material selected from the group consisting of ONO, tantalum oxide, barium strontium titanate and silicon nitride; a second polysilicon layer over the dielectric layer; a barrier layer over the second polysilicon layer comprising a metal nitride; a metal layer over the barrier layer comprising a refractory metal selected from the group consisting of titanium, tungsten, tantalum, cobalt and molybdenum; a nitride layer over the metal layer; an oxidation barrier comprising nitride adjacent sidewalls of at least the metal layer; and a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer.

Claim 56

An electronic system, comprising: a processor; and a circuit module having a plurality of leads coupled to the processor, and further having a semiconductor die coupled to at least a portion of the plurality of leads, wherein the semiconductor die comprises: a substrate; and an integrated circuit supported by the substrate and having at least one floating gate stack, the at least one floating gate stack comprising: a first polysilicon layer; a dielectric layer over the first polysilicon layer comprising a dielectric material selected from the group consisting of ONO, tantalum oxide, barium strontium titanate and silicon nitride; a second polysilicon layer over the dielectric layer; a barrier layer over the second polysilicon layer comprising a metal nitride; a metal layer over the barrier layer comprising a refractory metal selected from the group consisting of titanium, tungsten, tantalum, cobalt and molybdenum; a nitride layer over the metal layer; an oxidation barrier comprising nitride adjacent sidewalls of at least the metal layer; and a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer.

Claim 57

An electronic system, comprising: a processor; and a circuit module having a plurality of leads coupled to the processor, and further having a semiconductor die coupled to at least a portion of the plurality of leads, wherein the semiconductor die comprises: a substrate; and an integrated circuit supported by the substrate and having at least one floating gate stack, the at least one floating gate stack comprising: a first polysilicon layer; a second polysilicon layer; a dielectric layer comprising a dielectric material selected from the group consisting of ONO, tantalum oxide, barium strontium titanate and silicon nitride, and interposed between the first polysilicon layer and the second polysilicon layer; a metal layer comprising a refractory metal selected from the group consisting of titanium, tungsten, tantalum, cobalt and molybdenum; a barrier layer comprising a metal nitride and interposed between the metal layer and the second polysilicon layer; a nitride layer over the metal layer; an oxidation barrier comprising nitride adjacent sidewalls of at least the metal layer; and a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer.

Claim 58

An electronic system, comprising: a processor; and a circuit module having a plurality of leads coupled to the processor, and further having a semiconductor die coupled to at least a portion of the plurality of leads, wherein the semiconductor die comprises: a substrate; and an integrated circuit supported by the substrate and having at least one floating gate stack, the at least one floating gate stack comprising: a first polysilicon layer; a second polysilicon layer; a dielectric layer comprising a dielectric material selected from the group consisting of ONO, tantalum oxide, barium strontium titanate and silicon nitride, and interposed between the first polysilicon layer and the second polysilicon layer; a metal layer comprising a refractory metal selected from the group consisting of titanium, tungsten, tantalum, cobalt and molybdenum; a barrier layer comprising a metal nitride and interposed between the metal layer and the second polysilicon layer; a nitride layer over the metal layer; an oxidation barrier comprising nitride adjacent sidewalls of at least the metal layer; and a sidewall oxide layer adjacent sidewalls of at least the first polysilicon layer.