Non-volatile semiconductor memory device

Claim 2

A non-volatile semiconductor memory device comprising: a p type source region and a p type drain region formed in a surface of an n type region of a semiconductor substrate, with a channel region therebetween; a layer stack overlying the channel region and comprising, in overlying sequence from the channel region: a first insulating layer comprising a tunnel oxide film; a floating gate charge storage electrode layer; a second insulating layer; and a control gate electrode layer, wherein each of the layers comprising the layer stack is coextensive with the other layers of the layer stack; and data program means for programming the memory device with data, the data program means including means for injecting electrons from within the drain region to the floating gate charge storage electrode by hot electron injection induced by a band-to-band tunnel current.

Claim 3

The non-volatile semiconductor memory device as recited in claim 1 , further comprising data erasure means for erasing data, said data erasure means including means for ejecting electrons from said charge storage electrode to said channel region by an FN tunnel phenomenon.

Claim 4

The non-volatile semiconductor memory device as recited in claim 1 , wherein an edge of each of the source and drain regions extends beneath the respective adjacent edge of the layer stack.

Claim 5

A non-volatile semiconductor memory device comprising: a p type source region and a p type drain region formed in a surface of an n type region of a semiconductor substrate, with a channel region therebetween; a layer stack overlying the channel region and comprising, in overlying sequence from the channel region: a first insulating layer comprising a tunnel oxide film; a floating gate charge storage electrode layer; a second insulating layer; and a control gate electrode layer, wherein each of the layers comprising the layer stack is coextensive with the other layers of the layer stack; and data program means for programming the memory device with data, the data program means including means for injecting electrons from within the drain region to the floating gate charge storage electrode without avalanche breakdown, comprising: negative potential applying means for applying to the drain region a potential more negative than the substrate potential; and positive potential applying means for applying to the control electrode a potential more positive than the substrate potential.

Claim 6

A non-volatile semiconductor memory device comprising: a p type source region and a p type drain region formed in a surface of an n type region of a semiconductor substrate, with a channel region therebetween; a layer stack overlying the channel region and comprising, in overlying sequence from the channel region: a first insulating layer comprising a tunnel oxide film; a floating gate charge storage electrode layer; a second insulating layer; and a control gate electrode layer, wherein each of the layers comprising the layer stack is coextensive with the other layers of the layer stack; and data program means for programming the memory device with data, the data program means including means for injecting electrons from within the drain region to the floating gate charge storage electrode without avalanche breakdown, comprising: negative potential applying means for applying to the drain region a potential more negative than the substrate potential; and positive potential applying means for applying to the control electrode a potential more positive than the substrate potential.

Claim 7

The non-volatile semiconductor memory device as recited in claim 4 , said data program means further including: means for bringing the potential of said source region to an open state, and means for bringing the potential of said n type region to a ground state.

Claim 8

The non-volatile semiconductor memory device as recited in claim 4 , wherein said channel region includes a p type buried layer.

Claim 9

The non-volatile semiconductor memory device as recited in claim 4 , wherein said charge storage electrode is formed of n type polysilicon.

Claim 10

The non-volatile semiconductor memory device as recited in claim 4 , wherein said charge storage electrode is formed of p type polysilicon.

Claim 11

The non-volatile semiconductor memory device as recited in claim 4 , wherein a portion of said drain region under said charge storage electrode has a p type dopant impurity concentration of at most 5×10 19 cm −3 .

Claim 12

The non-volatile semiconductor memory device as recited in claim 4 , wherein a portion of said drain region under said charge storage electrode has an type dopant impurity concentration of at least 5×10 19 cm −3 , and a portion of said source region under said charge storage electrode has a p type dopant impurity concentration of at most 5×10 19 cm −3 .

Claim 13

The non-volatile semiconductor memory device as recited in claim 4 , wherein said channel region includes: a first impurity doped region in contact with said source region and having a p type dopant impurity concentration lower than the p type dopant impurity concentration of said source region, and a second impurity dopant region formed in contact with said drain region and having a p type dopant impurity concentration lower than the p type dopant impurity concentration of said drain region.

Claim 14

The non-volatile semiconductor memory device as recited in claim 4 , wherein said n type region includes an n + type impurity region formed in contact with said drain region so as to surround said drain region.

Claim 15

The non-volatile semiconductor memory device as recited in claim 4 , wherein said source region and said drain region are structured in symmetry to said charge storage electrode and said control electrode.

Claim 16

The non-volatile semiconductor memory device as recited in claim 4 , wherein said first insulating film has a thickness of at most 15 nm.

Claim 17

The non-volatile semiconductor memory device as recited in claim 4 , wherein said p type source region, said p type drain region, said charge storage electrode, and said control gate electrode form a memory cell, said non-volatile semiconductor memory device comprising: a memory cell array including a plurality of said memory cells arranged in a plurality of rows and columns; a word line corresponding to said plurality of rows, the control electrode of said each memory cell being connected to said word line; and a bit line corresponding to said plurality of columns, the drain region of each said memory cell being connected to said bit line.

Claim 18

The non-volatile semiconductor memory device as recited in claim 15 , comprising a select gate transistor between said memory cell and said bit line.

Claim 19

The non-volatile semiconductor memory device as recited in claim 16 , wherein said select gate transistor is between said drain region of said memory cell and said bit line.

Claim 20

The non-volatile semiconductor memory device as recited in claim 15 , wherein said bit line includes a main bit line and a sub-bit line, said plurality of memory cells are divided into a plurality of sectors each including a plurality of memory cells arranged in a plurality of rows and columns, said non-volatile semiconductor memory device including a sub-bit line group provided corresponding to said plurality of sectors, and including a plurality of said sub-bit lines each corresponding to a plurality of columns in a corresponding sector, and a select transistor selectively connecting a plurality of said sub-bit line groups to a plurality of said main bit lines, said select transistor being a p channel type transistor.

Claim 21

The non-volatile semiconductor memory device as recited in claim 18 , wherein said sub-bit line is made of a metal interconnection material.

Claim 22

The non-volatile semiconductor memory device as recited in claim 15 , further comprising a peripheral circuit region in which a peripheral circuit for controlling operation of said memory cell is formed, wherein said peripheral circuit region includes a p channel type MOS transistor, and said source region and said drain region of said memory cell have the same structure as a source region and a drain region constituting said p channel type MOS transistor.

Claim 23

The non-volatile semiconductor memory device as recited in claim 15 , wherein said memory cell has a threshold voltage lower than a read voltage of said memory cell after erasure of said memory cell with an ultraviolet ray.

Claim 24

The non-volatile semiconductor memory device as recited in claim 15 , wherein said memory cell has a threshold voltage higher than a read voltage of said memory cell after erasure of said memory cell with an ultraviolet ray.

Claim 25

The non-volatile semiconductor memory device as recited in claim 15 , wherein said negative potential applying means calculates in a Vd-Id characteristic (Vd: drain voltage, Id: drain current) a value Vd 1 of Vd satisfying {(logId)/Vd}″0 when the absolute value of Vd is increased, and applies a negative potential having the absolute value of Vd smaller than Vd, to said drain region, so that avalanche destruction will not occur in a selected memory cell and non-selected memory cells connected to the same bit line of the selected memory cell.

Claim 26

The non-volatile semiconductor memory device as recited in claim 15 , wherein a negative potential and a positive potential are respectively applied to said drain region and said electric charge storage electrode by said negative potential applying means and said positive potential applying means so that the maximum current consumption is at most 1 p A per one memory cell.

Claim 27

The non-volatile semiconductor memory device as recited in claim 4 , further comprising data erasure means for erasing data, said data erasure means including: negative potential applying means for applying a potential more negative than the potential of said n type region to said control electrode, and positive potential applying means for applying a potential more positive than the potential of said control electrode to said source region and said n type region.

Claim 28

The non-volatile semiconductor memory device as recited in claim 25 , said data erasure means further including means for bringing the potential of said drain region to an open state.

Claim 29

The non-volatile semiconductor memory device as recited in claim 4 , wherein said p type source region, said p type drain region, said charge storage electrode, and said control electrode form a memory cell, said non-volatile semiconductor memory device comprising: a memory cell array including a plurality of said memory cells arranged in a plurality of rows and columns; a plurality of main bit lines provided corresponding to said plurality of rows; a source line provided in common to said plurality of memory cells; said plurality of memory cells being divided into a plurality of sectors each including a plurality of memory cells arranged in a plurality of rows and columns; a plurality of sub-bit line groups provided corresponding to said plurality of sectors and including a plurality of sub-bit lines each corresponding to a plurality of columns in a corresponding sector; a select gate transistor selectively connecting said plurality of sub-bit line groups to said plurality of main bit lines; and read out means for reading out from a predetermined memory cell, said read out means including: first potential applying means for applying a first potential to said main bit line and said select gate transistor which are not selected, said source line, and said n type region, second potential applying means for applying a potential lower than said first potential by 1 to 2 V to said main bit line and said sub-bit line which are selected, means for bringing the potential of a non-selected sub-bit line to an open state; and third potential applying means for applying a second potential to said select gate transistor which is selected.

Claim 30

The non-volatile semiconductor memory device as recited in claim 27 , wherein said first potential is an external power supply potential having a positive value, and said second potential is a ground potential.

Claim 31

The non-volatile semiconductor memory device as recited in claim 27 , wherein said first potential is a ground potential, and said second potential is an external power supply potential having a negative value.

Claim 32

The non-volatile semiconductor memory device as recited in claim 4 , wherein said p type source region, said p type drain region, said electric charge storage electrode and said control form a memory cell, said non-volatile semiconductor memory device comprising: a memory cell array including a plurality of said memory cells arranged in a plurality of rows and column; a word line corresponding to said plurality of rows, the control electrode of said each memory cell being connected to said word line; a bit line corresponding to said plurality of columns, the drain region of said each memory cell being connected to said bit line; a source line to which the source region of said each memory cell is connected; and read out means for reading out from said predetermined memory cell, said read out means including first potential applying means for applying a first potential to said bit line and said word line which are not selected, said source line, and said n type region; second potential applying means for applying a potential lower than said first potential by 1 to 2 V to said bit line which is selected; and third potential applying means for applying a second potential to said word line which is selected.

Claim 33

The non-volatile semiconductor memory device as recited in claim 30 , wherein said first potential is an external power supply potential having a positive value, and said second potential is a ground potential.

Claim 34

The non-volatile semiconductor memory device as recited in claim 30 , wherein said first potential is a ground potential, and said second potential is an external power supply potential having a negative value.

Claim 35

The non-volatile semiconductor memory device as recited in claim 4 , wherein an edge of each of the source and drain regions extends beneath the respective adjacent edge of the layer stack.