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US5596528A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of using source bias to raise threshold voltages and/or to compact threshold voltages

Assignee: Texas Instruments Inc
•
Filing: 1995-09-22
•
Granted: 1997-01-21
•
Expires: 2015-09-22
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Abstract

Abstract The method of this invention allows use of a smaller wordline voltage Vp1 during programming. In addition, the method results in a relatively narrow distribution of threshold voltages Vt when used to flash program an array of memory cells (10). The method of this invention increases compaction gate-current efficiency by reverse biasing the source (11)/substrate (23) junction of the cell being programmed. The reverse biasing is accomplished, for example, by applying a bias voltage to the source (11) or by placing a diode (27), a resistor (29) or other impedance in series with the source (11). The reverse biasing limits the source current (Is) of cell being programmed and of the entire array during flash-programming compaction.

Inventors

  • 👤 Cetin Kaya
  • 👤 Wayland B. Holland
  • 👤 Rabah Mezenner

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 14:11
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/12

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 93 words
A method for increasing the thresttold voltage of at least one of a plurality of floating-gate memory cells in a nonvolatile integrated-circuit memory having a substrate connected to a reference voltage, each said memory cell being of the single-transistor, non-slit-gate type, said method comprising: connecting the sources of said plurality of memory cells to a high impedance; causing currents to flow into the drains of said plurality memory cells; and placing a voltage on the control gates of said plurality of memory cells, said voltage being positive with respect to said reference voltage.
Claim 2
Independent Claim 93 words
A method for increasing the thresttold voltage of at least one of a plurality of floating-gate memory cells in a nonvolatile integrated-circuit memory having a substrate connected to a reference voltage, each said memory cell being of the single-transistor, non-slit-gate type, said method comprising: connecting the sources of said plurality of memory cells to a high impedance; causing currents to flow into the drains of said plurality memory cells; and placing a voltage on the control gates of said plurality of memory cells, said voltage being positive with respect to said reference voltage.
Claim 3
Dependent Claim 20 words
The method of claim 1, wherein a field-effect transistor in an "OFF" state is used to attain said high impedance.
Claim 4
Dependent Claim 66 words
The method of claim 1, wherein said plurality of memory cells is 10,000 of said memory cells, wherein a current of 100 microamperes is caused to flow into the parallel-connected drains of said plurality of memory cells and wherein said voltage on the control gates of said plurality memory cells is +5 volts with respect to said reference voltage, both for a period of one second.
Claim 5
Dependent Claim 17 words
The method of claim 1, wherein said plurality of memory cells is a column of memory cells.
Claim 6
Dependent Claim 20 words
The method of claim 1, said memory further having a ground voltage, wherein said reference voltage is said ground voltage.

References Cited (Backward Citations)

US5218571A Cited
US5272669A Cited
US5481494A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-01-21 2000-07-22 2001-01-21 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-01-21 2004-07-22 2005-01-21 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-01-21 2008-07-22 2009-01-21 $7700.00 Window Closed / Lapsed

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