US5477072A
Expired / Lapsed
US
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Nonvolatile semiconductor memory device
Assignee: SK Hynix Inc
•
Filing: 1994-11-16
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Granted: 1995-12-19
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Expires: 2014-11-16
Abstract
Abstract An EEPROM cell and a method for fabricating the same are disclosed. The EEPROM cell fabricated by the method comprises of: a first active region with a second conductive low density impurity formed in a first conductive semiconductor substrate; a second active region with a second conductive high density impurity formed in one side of said first active region; a third active region with the second conductive high density impurity formed in the other side of said first active region; a fourth active region with a first conductive high density impurity formed so as to surround said third active region; a floating gate atop a first insulating layer overlying said first active region; and a control gate atop a second insulating layer overlying said floating gate. The EEPROM cell is improved in an operational characteristic such as an erasing speed and a programming speed. The EEPROM cell is fabricated in such very small size to be integrated in a high integration degree. The method for fabricating the EEPROM cell according to the invention is simpler than the conventional ones, whereby the EEPROM cell can be easily fabricated.
Inventors
- 👤 Jung S. Goo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 17:50
CPC Classifications
H; H10; H10B; H10B41/00; H10B69/00; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
121 words
A nonvolatile semiconductor memory device, comprising: a p-type semiconductor substrate; a first active low-density n-type impurity region formed in said semiconductor substrate; a second active high-density n-type impurity region formed at one side of said first active region; a third active high-density n-type impurity region formed at an opposite side of said first active region; a fourth active high-density p-type impurity region formed so as to surround said third active region and thereby isolate said first active region from said third active region; a first insulating layer overlying said first active region; a floating gate on top of said first insulating layer; a second insulating layer overlying said floating gate; and a control gate on top of said second insulating layer.
Claim 2
Dependent Claim
121 words
A nonvolatile semiconductor memory device, comprising: a p-type semiconductor substrate; a first active low-density n-type impurity region formed in said semiconductor substrate; a second active high-density n-type impurity region formed at one side of said first active region; a third active high-density n-type impurity region formed at an opposite side of said first active region; a fourth active high-density p-type impurity region formed so as to surround said third active region and thereby isolate said first active region from said third active region; a first insulating layer overlying said first active region; a floating gate on top of said first insulating layer; a second insulating layer overlying said floating gate; and a control gate on top of said second insulating layer.
Claim 3
Dependent Claim
14 words
The device of claim 1 wherein said first active region is formed by ion-implantation.
Claim 4
Dependent Claim
23 words
The device of claim 1 wherein said second active region functions as a source and said third active region functions as a drain.
Claim 5
Dependent Claim
29 words
The device of claim 1 further comprising a fifth active low-density p-type region surrounding said fourth active region, and wherein said first active region surrounds said second active region.
Claim 6
Dependent Claim
30 words
The device of claim 1 further comprising an n + /p + drain side junction and an n - /p + source side junction, both associated with said semiconductor substrate.
Claim 7
Dependent Claim
19 words
The device of claim 1 wherein said second and third active regions are deeper than said first active region.
Claim 8
Dependent Claim
19 words
The device of claim 1 wherein said first active region is deeper than said second and third active regions.
Claim 9
Dependent Claim
15 words
The device of claim 1 wherein said first active region surrounds said second active region.
Claim 10
Dependent Claim
16 words
The device of claim 1 further comprising a fifth active region surrounding said fourth active region.
Claim 11
Dependent Claim
15 words
The device of claim 9 wherein said fifth active region is a low-density p-type region.
Claim 12
Dependent Claim
34 words
The device of claim 1 wherein the impurity density of said fourth active region is higher than that of said first active region and lower than those of said second and third active regions.
Claim 13
Dependent Claim
17 words
The device of claim 1 wherein said fourth active region does not surround said second insulating layer.
Claim 14
Dependent Claim
25 words
The device of claim 1 wherein a block junction between a source region of said device and a drain region of said device is provided.
Claim 15
Dependent Claim
115 words
A nonvolatile semiconductor memory device, comprising: a p-type semiconductor substrate; a first active low-density n-type impurity region formed in said semiconductor substrate; a second active high-density n-type impurity region formed at one side of said first active region; a third active high-density n-type impurity region formed at an opposite side of said first active region; a fourth active high-density p-type impurity region formed so as to surround said third active region but not said second active region; a first insulating layer overlying said first active region; a floating gate on top of said first insulating layer; a second insulating layer overlying said floating gate; and a control gate on top of said second insulating layer.
Claim 16
Dependent Claim
115 words
A nonvolatile semiconductor memory device, comprising: a p-type semiconductor substrate; a first active low-density n-type impurity region formed in said semiconductor substrate; a second active high-density n-type impurity region formed at one side of said first active region; a third active high-density n-type impurity region formed at an opposite side of said first active region; a fourth active high-density p-type impurity region formed so as to surround said third active region but not said second active region; a first insulating layer overlying said first active region; a floating gate on top of said first insulating layer; a second insulating layer overlying said floating gate; and a control gate on top of said second insulating layer.
Claim 17
Dependent Claim
14 words
The device of claim 14 wherein said first active region is formed by ion-implantation.
Claim 18
Dependent Claim
23 words
The device of claim 14 wherein said second active region functions as a source and said third active region functions as a drain.
Claim 19
Dependent Claim
29 words
The device of claim 14 further comprising a fifth active low-density p-type region surrounding said fourth active region, and wherein said first active region surrounds said second active region.
Claim 20
Dependent Claim
30 words
The device of claim 14 further comprising an n + /p + drain side junction and an n - /p + source side junction, both associated with said semiconductor substrate.
Claim 21
Dependent Claim
19 words
The device of claim 14 wherein said second and third active regions are deeper than said first active region.
Claim 22
Dependent Claim
19 words
The device of claim 14 wherein said first active region is deeper than said second and third active regions.
Claim 23
Dependent Claim
15 words
The device of claim 14 wherein said first active region surrounds said second active region.
Claim 24
Dependent Claim
16 words
The device of claim 14 further comprising a fifth active region surrounding said fourth active region.
Claim 25
Dependent Claim
15 words
The device of claim 22 wherein said fifth active region is a low-density p-type region.
Claim 26
Dependent Claim
34 words
The device of claim 14 wherein the impurity density of said fourth active region is higher than that of said first active region and lower than those of said second and third active regions.
Claim 27
Dependent Claim
25 words
The device of claim 14 wherein a block junction between a source region of said device and a drain region of said device is provided.
Claim 28
Dependent Claim
130 words
A nonvolatile semiconductor memory device, comprising: a p-type semiconductor substrate; a first active low-density n-type impurity region formed in said semiconductor substrate; a second active high-density n-type impurity region formed at one side of said first active region; a third active high-density n-type impurity region formed at an opposite side of said first active region; a fourth active high-density p-type impurity region formed so as to surround said third active region; a first insulating layer overlying said first active region; a floating gate on top of said first insulating layer; a second insulating layer overlying said floating gate; a control gate on top of said second insulating layer; and a fifth active low-density p-type region surrounding said fourth active region, and said first active region surrounds said second active region.
Claim 29
Dependent Claim
130 words
A nonvolatile semiconductor memory device, comprising: a p-type semiconductor substrate; a first active low-density n-type impurity region formed in said semiconductor substrate; a second active high-density n-type impurity region formed at one side of said first active region; a third active high-density n-type impurity region formed at an opposite side of said first active region; a fourth active high-density p-type impurity region formed so as to surround said third active region; a first insulating layer overlying said first active region; a floating gate on top of said first insulating layer; a second insulating layer overlying said floating gate; a control gate on top of said second insulating layer; and a fifth active low-density p-type region surrounding said fourth active region, and said first active region surrounds said second active region.
Claim 30
Dependent Claim
122 words
A nonvolatile semiconductor memory device, comprising: a p-type semiconductor substrate; a first active low-density n-type impurity region formed in said semiconductor substrate; a second active high-density n-type impurity region formed at one side of said first active region; a third active-high density n-type region formed at an opposite side of said first active region; wherein said first active region is deeper than said second and third active regions; a fourth active high-density p-type impurity region formed so as to surround said third active region; a first insulating layer overlying said first active region; a floating gate on top of said first insulating layer; a second insulating layer overlying said floating gate; and a control gate on top of said second insulating layer.
Claim 31
Dependent Claim
122 words
A nonvolatile semiconductor memory device, comprising: a p-type semiconductor substrate; a first active low-density n-type impurity region formed in said semiconductor substrate; a second active high-density n-type impurity region formed at one side of said first active region; a third active-high density n-type region formed at an opposite side of said first active region; wherein said first active region is deeper than said second and third active regions; a fourth active high-density p-type impurity region formed so as to surround said third active region; a first insulating layer overlying said first active region; a floating gate on top of said first insulating layer; a second insulating layer overlying said floating gate; and a control gate on top of said second insulating layer.
Claim 32
Dependent Claim
119 words
A nonvolatile semiconductor memory device, comprising: a p-type semiconductor substrate; a first active low-density n-type impurity region formed in said semiconductor substrate; a second active high-density n-type impurity region formed at one side of said first active region; wherein said first active region surrounds said second active region; a third active high-density n-type impurity region formed at an opposite side of said first active region; a fourth active high-density p-type impurity region formed so as to surround said third active region; a first insulating layer overlying said first active region; a floating gate on top of said first insulating layer; a second insulating layer overlying said floating gate; and a control gate on top of said second insulating layer.
Claim 33
Dependent Claim
119 words
A nonvolatile semiconductor memory device, comprising: a p-type semiconductor substrate; a first active low-density n-type impurity region formed in said semiconductor substrate; a second active high-density n-type impurity region formed at one side of said first active region; wherein said first active region surrounds said second active region; a third active high-density n-type impurity region formed at an opposite side of said first active region; a fourth active high-density p-type impurity region formed so as to surround said third active region; a first insulating layer overlying said first active region; a floating gate on top of said first insulating layer; a second insulating layer overlying said floating gate; and a control gate on top of said second insulating layer.
Claim 34
Dependent Claim
120 words
A nonvolatile semiconductor device, comprising: a p-type semiconductor substrate; a first active low-density n-type impurity region formed in said semiconductor substrate; a second active high-density n-type impurity region formed at one side of said first active region; a third active high-density n-type impurity region formed at an opposite side of said first active region; a fourth active high-density p-type impurity region formed so as to surround said third active region; a first insulating layer overlying said first active region; a floating gate on top of said first insulating layer; a second insulating layer overlying said floating gate; a control gate on top of said second insulating layer; and a fifth active low-density p-type impurity region surrounding said fourth active region.
Claim 35
Dependent Claim
120 words
A nonvolatile semiconductor device, comprising: a p-type semiconductor substrate; a first active low-density n-type impurity region formed in said semiconductor substrate; a second active high-density n-type impurity region formed at one side of said first active region; a third active high-density n-type impurity region formed at an opposite side of said first active region; a fourth active high-density p-type impurity region formed so as to surround said third active region; a first insulating layer overlying said first active region; a floating gate on top of said first insulating layer; a second insulating layer overlying said floating gate; a control gate on top of said second insulating layer; and a fifth active low-density p-type impurity region surrounding said fourth active region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-12-18 | 1999-06-19 | 1999-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-18 | 2003-06-19 | 2003-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-18 | 2007-06-19 | 2007-12-19 | $7700.00 | Window Closed / Lapsed |