Method of manufacturing a semiconductor integrated circuit device

Claim 1

A method of a fabricating a semiconductor integrated circuit device comprising the steps of: simultaneously forming first and second gate insulation films at one part and another part of the main surface of a first conductivity type semiconductor substrate, respectively; forming a conductor layer on said first and second gate insulation films and patterning said conductor layer thereby to form first and second gate electrodes; forming an insulation film on said first gate electrode; forming a third gate electrode on said insulation film of said first gate electrode; and introducing into said substrate an impurity which determines a second conductivity type exhibiting the opposite conductivity to said first conductivity type thereby to form source and drain regions.

Claim 2

A method of a fabricating a semiconductor integrated circuit device comprising the steps of: simultaneously forming first and second gate insulation films at one part and another part of the main surface of a first conductivity type semiconductor substrate, respectively; forming a conductor layer on said first and second gate insulation films and patterning said conductor layer thereby to form first and second gate electrodes; forming an insulation film on said first gate electrode; forming a third gate electrode on said insulation film of said first gate electrode; and introducing into said substrate an impurity which determines a second conductivity type exhibiting the opposite conductivity to said first conductivity type thereby to form source and drain regions.

Claim 8

A method of fabricating a semiconductor integrated circuit comprising: (a) oxidizing the surface of a P type single crystalline substrate to form a silicon dioxide film and forming a silicon nitride film on the silicon dioxide film; (b) selectively etching the silicon nitride film and introducing an impurity through the silicon dioxide to form P+ channel stoppers; (c) oxidizing the areas which were selectively etched to form a silicon dioxide field film at each of said areas; (d) removing the remaining silicon nitride and underlying silicon dioxide films and again oxidizing said substrate to form silicon dioxide gate films; (e) introducing an impurity into the substrate through said gate films to control the threshold voltage levels; (f) introducing an impurity which will establish an N type region into the part of the surface where it is desired to form depletion MIS transistors and enhancement MIS transistors with a high break down voltage; (g) introducing an impurity which will form a P+ region into the part of the substrate where memory transistors are to be formed; (h) forming a first polycrystalline layer over the silicon dioxide layer on said substrate; (i) selectively etching said polycrystalline layer to form the gates of the peripheral transistors and a first wiring layer; (j) introducing an impurity which will increase conductivity into said gates and first wiring layer; (k) oxidizing said substrate to form silicon dioxide films over said gates and wiring layers; (l) forming a second polycrystalline layer on said substrate and etching said layer and said underlying silicon dioxide and first polycrystalline layers to form control gate electrodes and floating gate electrodes for the memory transistors; (m) introducing an impurity which will increase conductivity into said control gate electrodes; (n) further etching said second polycrystalline layer to form second and third wiring layers and to form an offset gate electrode for the MIS transistor with high breakdown voltage; (o) introducing an impurity to form source and drain regions for the transistors; (p) etching the silicon dioxide film over the source and drain regions; (q) forming a phosphosilicate glass film on said substrate; (r) etching said glass film to form contact holes to said source and drain regions; and (s) vaporizing a patterned metal onto said substrate and into said contact holes.

Claim 9

A method of fabricating a semiconductor integrated circuit comprising: (a) oxidizing the surface of a P type single crystalline substrate to form a silicon dioxide film and forming a silicon nitride film on the silicon dioxide film; (b) selectively etching the silicon nitride film and introducing an impurity through the silicon dioxide to form P+ channel stoppers; (c) oxidizing the areas which were selectively etched to form a silicon dioxide field film at each of said areas; (d) removing the remaining silicon nitride and underlying silicon dioxide films and again oxidizing said substrate to form silicon dioxide gate films; (e) introducing an impurity into the substrate through said gate films to control the threshold voltage levels; (f) introducing an impurity which will establish an N type region into the part of the surface where it is desired to form depletion MIS transistors and enhancement MIS transistors with a high break down voltage; (g) introducing an impurity which will form a P+ region into the part of the substrate where memory transistors are to be formed; (h) forming a first polycrystalline layer over the silicon dioxide layer on said substrate; (i) selectively etching said polycrystalline layer to form the gates of the peripheral transistors and a first wiring layer; (j) introducing an impurity which will increase conductivity into said gates and first wiring layer; (k) oxidizing said substrate to form silicon dioxide films over said gates and wiring layers; (l) forming a second polycrystalline layer on said substrate and etching said layer and said underlying silicon dioxide and first polycrystalline layers to form control gate electrodes and floating gate electrodes for the memory transistors; (m) introducing an impurity which will increase conductivity into said control gate electrodes; (n) further etching said second polycrystalline layer to form second and third wiring layers and to form an offset gate electrode for the MIS transistor with high breakdown voltage; (o) introducing an impurity to form source and drain regions for the transistors; (p) etching the silicon dioxide film over the source and drain regions; (q) forming a phosphosilicate glass film on said substrate; (r) etching said glass film to form contact holes to said source and drain regions; and (s) vaporizing a patterned metal onto said substrate and into said contact holes.