US4326329A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making a contact programmable double level polysilicon MOS read only memory
Assignee: Texas Instruments Inc
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Filing: 1980-02-28
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Granted: 1982-04-27
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Expires: 2000-02-28
Abstract
Abstract A contact programmable, small cell area MOS read only memory or ROM is formed by a process compatible with standard N-channel silicon gate manufacturing methods. Address lines are metal, gates are second level polysilicon, and output and ground lines are defined by elongated N+ regions. Each potential MOS transistor in the array is programmed to be a logic "1" or "0", by presence or absence of a contact engaging the polysilicon gate over the thin gate oxide.
Inventors
- 👤 David J. McElroy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 03:25
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12; G11C17/126; H10B; H10B20/00; H10W20/40
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
148 words
A method of making a read-only-memory which includes the steps of: forming a plurality of insulated gate field effect transistors in a face of a semiconductor body, each of the transistors having a source-to-drain path and a gate, the transistors being in a regular pattern of rows and columns to provide an array of memory cells; applying segments of polycrystalline silicon to said face to provide separate gates for the transistors; applying an insulating coating to the face over said gates; selectively removing said insulating coating from some of the gates; applying strips of conductive material to the face insulated from the gates by said insulating coating; except where selectively removed; the memory being programmed by said opening of apertures in the insulating coating before applying the conductive material, the apertures directly overlying the gates and source-to-drain paths and being opened over only selected ones of the transistors.
Claim 2
Independent Claim
148 words
A method of making a read-only-memory which includes the steps of: forming a plurality of insulated gate field effect transistors in a face of a semiconductor body, each of the transistors having a source-to-drain path and a gate, the transistors being in a regular pattern of rows and columns to provide an array of memory cells; applying segments of polycrystalline silicon to said face to provide separate gates for the transistors; applying an insulating coating to the face over said gates; selectively removing said insulating coating from some of the gates; applying strips of conductive material to the face insulated from the gates by said insulating coating; except where selectively removed; the memory being programmed by said opening of apertures in the insulating coating before applying the conductive material, the apertures directly overlying the gates and source-to-drain paths and being opened over only selected ones of the transistors.
Claim 3
Dependent Claim
25 words
A method according to claim 1 including forming a plurality of N-channel silicon gate transistors in the face peripheral to the array of memory cells.
Claim 4
Dependent Claim
34 words
A method according to claim 2 wherein the gates of the transistors in the memory array are formed during the same step as formation of the gates of the transistors peripheral to the array.
Claim 5
Dependent Claim
60 words
A method according to claim 3 wherein the source regions of the transistors in the periphery are formed by diffusion using oxide underlying the gates of such transistors as a mask, while the source and drain regions of the transistors in the array are formed prior to deposition of polycrystalline silicon to form the gates of the memory array transistors.
Claim 6
Dependent Claim
27 words
A method according to claim 4 wherein a thick layer of thermal oxide is formed over the source and drain regions of the transistors in the array.
Claim 7
Independent Claim
148 words
A method of making a read-only-memory which includes the steps of: forming a plurality of insulated gate field effect transistors in a face of a semiconductor body, each of the transistors having a source-to-drain path and a gate and having source and drain regions in said face beneath thick thermal oxide, the transistors being in a regular pattern of rows and columns to provide an array of memory cells; applying segments of conductive material to said face to provide separate gates for the transistors; applying an insulating coating over said gates and patterning the insulating coating to define apertures; applying the strips of conductive material to the face over the gates; the memory being programmed by the said apertures formed in the insulating coating before applying the conductive material, the apertures directly overlying the gates and source-to-drain paths and being opened over only selected ones of the transistors.
Claim 8
Independent Claim
148 words
A method of making a read-only-memory which includes the steps of: forming a plurality of insulated gate field effect transistors in a face of a semiconductor body, each of the transistors having a source-to-drain path and a gate and having source and drain regions in said face beneath thick thermal oxide, the transistors being in a regular pattern of rows and columns to provide an array of memory cells; applying segments of conductive material to said face to provide separate gates for the transistors; applying an insulating coating over said gates and patterning the insulating coating to define apertures; applying the strips of conductive material to the face over the gates; the memory being programmed by the said apertures formed in the insulating coating before applying the conductive material, the apertures directly overlying the gates and source-to-drain paths and being opened over only selected ones of the transistors.
Claim 9
Dependent Claim
25 words
A method according to claim 6 including forming a plurality of N-channel silicon gate transistors in the face peripheral to the array of memory cells.
Claim 10
Dependent Claim
33 words
A method according to claim 7 wherein the gates of the transistors in the memory array are formed by the step of formation of the gates of the transistors peripheral to the array.
Claim 11
Dependent Claim
56 words
A method according to claim 8 wherein the source regions of the transistors in the periphery are formed by diffusion using oxide underlying the gates of such transistors as a mask, while the source and drain regions of the transistors in the array are formed prior to deposition of the gates of the memory array transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-04-26 | 1985-10-26 | 1986-04-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-04-26 | 1989-10-26 | 1990-04-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-04-26 | 1993-10-26 | 1994-04-27 | $7700.00 | Window Closed / Lapsed |