US4208781A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit with implanted resistor element in polycrystalline silicon layer
Assignee: Texas Instruments Inc
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Filing: 1978-06-15
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Granted: 1980-06-24
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Expires: 1998-06-15
Abstract
Abstract Resistor elements for MOS integrated circuits are made by an ion implant step compatible with a self-aligned N-channel silicon-gate process. The resistor elements are in a part of a polycrystalline silicon layer which is also used as a gate for an MOS transistor and as an interconnection overlying field oxide. Resistors of this type are ideally suited for load devices in static RAM cells.
Inventors
- 👤 G. R. Mohan Rao
- 👤 John S. Stanczak
- 👤 Jih-Chang Lien
- 👤 Shyam Bhatia
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 14:30
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10B; H10B10/00; H10B10/15; H10P; H10P32/00; H10P32/30; H10P32/302; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/40; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49082
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
148 words
A method of making resistor elements in an insulated-gate field effect transistor integrated circuit comprising the steps of: (a) forming thick field oxide in a pattern on the face of a semiconductor substrate, the field oxide surrounding a plurality of areas containing transistors, (b) depositing relatively pure polycrystalline silicon over the field oxide and extending over at least some of the plurality of areas, (c) implanting conductivity-determining impurity material into the polycrystalline silicon to provide resistor regions, of resistivity lower than that of the polycrystalline silicon when deposited, (d) introducing conductivity-determining impurity material into other areas of the polycrystalline silicon exclusive of said resistor regions at an impurity concentration much higher than that of the resistor regions to provide connections to the transistors and to provide interconnections to other circuit elements of the integrated circuit, (e) patterning said polycrystalline silicon to define said regions and said other areas.
Claim 2
Independent Claim
148 words
A method of making resistor elements in an insulated-gate field effect transistor integrated circuit comprising the steps of: (a) forming thick field oxide in a pattern on the face of a semiconductor substrate, the field oxide surrounding a plurality of areas containing transistors, (b) depositing relatively pure polycrystalline silicon over the field oxide and extending over at least some of the plurality of areas, (c) implanting conductivity-determining impurity material into the polycrystalline silicon to provide resistor regions, of resistivity lower than that of the polycrystalline silicon when deposited, (d) introducing conductivity-determining impurity material into other areas of the polycrystalline silicon exclusive of said resistor regions at an impurity concentration much higher than that of the resistor regions to provide connections to the transistors and to provide interconnections to other circuit elements of the integrated circuit, (e) patterning said polycrystalline silicon to define said regions and said other areas.
Claim 3
Dependent Claim
32 words
A method according to claim 1 wherein the implanting of impurity material is at a dosage equivalent to 5×10 13 to 1×10 14 ions per CM 2 at 100 to 150 KeV.
Claim 4
Dependent Claim
26 words
A method according to claim 2 wherein the impurity material is phosphorus and the thickness of the polycrystalline silicon is no more than about 0.5 micron.
Claim 5
Dependent Claim
16 words
A method according to claim 2 wherein the step of introducing impurity material includes phosphorus diffusion.
Claim 6
Dependent Claim
34 words
A method according to claim 1 wherein a coating is applied over the resistor regions of the polycrystalline silicon after implanting impurity material, the coating consisting of thermal silicon oxide or deposited silicon nitride.
Claim 7
Dependent Claim
21 words
A method according to claim 5 wherein the coating over the polycrystalline silicon functions to mask the introduction of impurity material.
Claim 8
Dependent Claim
26 words
A method according to claim 1 wherein the resistor regions are masked from said step of introducing impurity by a patterned coating over said polycrystalline silicon.
Claim 9
Dependent Claim
32 words
A method according to claim 1 wherein the transistors are of the N-channel type, the step of implanting employs an N-type impurity, and the step of introducing also employs an N-type impurity.
Claim 10
Dependent Claim
52 words
A method according to claim 8 wherein the step of introducing impurity material into said other areas of the polycrystalline silicon dopes gate areas of the transistors and also forms source and drain regions of the transistors in the face of the substrate, and the resistor regions are over the field oxide.
Claim 11
Dependent Claim
52 words
A method according to claim 1 wherein a coating is applied over a polycrystalline silicon after implanting impurity material, the coating consisting of thermal silicon oxide, then the coating is patterned to cover only the resistor regions and expose said other areas, and the step of introducing impurity material is by diffusion.
Claim 12
Independent Claim
140 words
A method of making resistor elements and conductive interconnections in a semiconductor integrated circuit, comprising the steps of: (a) forming an insulating coating on a face of a semiconductor body, the insulating coating surrounding areas of said face for active elements of the integrated circuit, (b) depositing relatively pure polycrystalline silicon on said face over said insulating coating and extending over at least some of said areas, (c) implanting conductivity-determining impurity material into the polycrystalline silicon to provide resistor regions of a resistivity lower than that of the polycrystalline silicon when deposited, and (d) selectively introducing conductivity-determining impurity material into other regions of the polycrystalline silicon exclusive of the resistor regions at an impurity concentration much higher than that of said resistor regions to provide connections from resistor regions to the active circuit elements and conductive interconnections between circuit elements.
Claim 13
Independent Claim
140 words
A method of making resistor elements and conductive interconnections in a semiconductor integrated circuit, comprising the steps of: (a) forming an insulating coating on a face of a semiconductor body, the insulating coating surrounding areas of said face for active elements of the integrated circuit, (b) depositing relatively pure polycrystalline silicon on said face over said insulating coating and extending over at least some of said areas, (c) implanting conductivity-determining impurity material into the polycrystalline silicon to provide resistor regions of a resistivity lower than that of the polycrystalline silicon when deposited, and (d) selectively introducing conductivity-determining impurity material into other regions of the polycrystalline silicon exclusive of the resistor regions at an impurity concentration much higher than that of said resistor regions to provide connections from resistor regions to the active circuit elements and conductive interconnections between circuit elements.
Claim 14
Dependent Claim
32 words
A method according to claim 11 wherein the active circuit elements are insulated gate field effect transistors and said polycrystalline silicon forms gates of the transistors by parts of said other regions.
Claim 15
Dependent Claim
27 words
A method according to claim 12 including the step of patterning the polycrystalline silicon by a photoresist operation to leave said resistor regions and said other regions.
Claim 16
Dependent Claim
35 words
A method according to claim 11 including the step of masking said resistor regions by a coating of thermal oxide over said polycrystalline silicon, and wherein the step of introducing impurity material is by diffusion.
Claim 17
Dependent Claim
39 words
A method according to claim 12 wherein said insulating coating is field oxide surrounding the transistors wherein oxide much thinner than said field oxide underlies said gates, and wherein said resistor regions at least partially overlie said field oxide.
References Cited (Backward Citations)
US3570114A
Cited
US4055444A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-06-24 | 1983-12-24 | 1984-06-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-06-24 | 1987-12-24 | 1988-06-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-06-24 | 1991-12-24 | 1992-06-24 | $7700.00 | Window Closed / Lapsed |