Abstract A method of making a metal oxide semiconductor large scale integration circuit incorporating both parallel and series gate matrix circuits using a self-alignment technique is provided, wherein a plurality of diffused regions of a conductivity type opposite to that of a silicon substrate are formed in the silicon substrate to extend substantially parallel to one another, a silicon dioxide layer as a field oxide layer is formed over the entire surface area of this structure, a hole is cut into the dioxide layer at each of selected portions thereof lying between the diffused regions, a gate oxide layer is formed in each of the holes, and then a plurality of gate electrode layers are strip shaped and located transverse to the diffused regions with each of the gate oxide layers having at least a portion of the associated gate electrode layer placed thereon, thereby providing a plurality of MOS field-effect transistors. This method makes it possible to produce parallel gate matrix circuits by the use of a diffusing mask for self-alignment as a mask pattern for forming the gate oxide layer.
A method for fabricating a parallel gate matrix circuit in a self-alignment type metal oxide semiconductor large scale integration circuit, said parallel gate matrix circuit including a silicon substrate, a plurality of diffused regions of opposite conductivity-type to that of the silicon substrate and a plurality of gate electrode layers arranged transversely to said diffused regions to form metal oxide semiconductor field-effect transistors at crosspoints thereof, said method comprising the steps of forming said plurality of diffused regions extending in parallel to each other; covering the entire area of the silicon substrate surface in which said diffused regions are fabricated with a field oxide film; then forming openings at required portions of the area of said field oxide film between said diffused regions simultaneously with the formation of diffusing windows using a diffusion mask for self-alignment; forming a gate oxide film in said openings; and thereafter forming a polycrystalline silicon or molybdenum gate electrode layer in transverse relation with said extended diffused regions, at least a portion of said gate electrode layer lying on said gate oxide film, whereby metal oxide semiconductor field-effect transistors are formed in only those areas where said gate oxide film is formed.
Claim 2
Independent Claim
197 words
A method for fabricating a parallel gate matrix circuit in a self-alignment type metal oxide semiconductor large scale integration circuit, said parallel gate matrix circuit including a silicon substrate, a plurality of diffused regions of opposite conductivity-type to that of the silicon substrate and a plurality of gate electrode layers arranged transversely to said diffused regions to form metal oxide semiconductor field-effect transistors at crosspoints thereof, said method comprising the steps of forming said plurality of diffused regions extending in parallel to each other; covering the entire area of the silicon substrate surface in which said diffused regions are fabricated with a field oxide film; then forming openings at required portions of the area of said field oxide film between said diffused regions simultaneously with the formation of diffusing windows using a diffusion mask for self-alignment; forming a gate oxide film in said openings; and thereafter forming a polycrystalline silicon or molybdenum gate electrode layer in transverse relation with said extended diffused regions, at least a portion of said gate electrode layer lying on said gate oxide film, whereby metal oxide semiconductor field-effect transistors are formed in only those areas where said gate oxide film is formed.