Mos transistor integrated matrix

Claim 2

A logic circuit comprising a semiconductor substrate, a matrix of input rows and output columns of substantially identical voltage controlled semiconductor devices each having a control electrode on said substrate, generally parallel input conductors forming input rows to said matrix for respectively and substantially simultaneously receiving a plurality of both true logic signals and the complements thereof, and respectively connecting in common the control electrode of each voltage controlled device in an input row, another electrode of each voltage control device in each output column being connected in common to form output terminals for said output columns, and a third electrode of each device connected to a common reference potential, the number of voltage controlled devices in at least one output column being less than the number of input conductors to said matrix for receiving said true logic signals, said voltage controlled devices in said matrix being selectively arrayed in rows and columns to produce at said output terminals signals representative of selected combinations of input signals on said input conductors.

Claim 3

A logic circuit comprising a substrate, a first matrix of input rows and output columns of voltage controlled devices on said substrate, generally parallel input conductors forming input rows to said first matrix and connecting in common the control electrode of each voltage controlled device in an input row, another electrode of each voltage control device in each output column being connected in common to form output terminals for said output columns, the number of voltage controlled devices in at least one output column being less than the number of independent input signals to said first matrix said voltage controlled devices in said first matrix being arrayed to produce at said output terminals signals representative of selected combinations of said input signals, a second matrix of input columns and output rows of said voltage controllEd devices on said substrate, generally parallel second input conductors connecting the control electrode of each voltage controlled device in an input column of said second matrix in common, another electrode of each voltage controlled device in an output row of said second matrix being connected in common to form output terminals for said output rows of said second matrix, means connecting a further electrode of each voltage controlled device in said second matrix in common, means connecting the output terminals of said first matrix to said second input conductors, said voltage controlled devices of said second matrix being arrayed in said second matrix to provide at the output terminals of said second matrix signals representative of selected combinations of the terms appearing at the output terminals of said first matrix.

Claim 4

A logic circuit comprising a substrate, a first matrix of input rows and output columns of voltage controlled devices on said substrate, generally parallel input conductors forming input rows to said first matrix and connecting in common the control electrode of each voltage controlled device in an input row, another electrode of each voltage control device in each output column being connected in common to form output terminals for said output columns, the number of voltage controlled devices in at least one output column being less than the number of independent input signals to said first matrix said voltage controlled devices in said first matrix being arrayed to produce at said output terminals signals representative of selected combinations of said input signals, a second matrix of input columns and output rows of said voltage controllEd devices on said substrate, generally parallel second input conductors connecting the control electrode of each voltage controlled device in an input column of said second matrix in common, another electrode of each voltage controlled device in an output row of said second matrix being connected in common to form output terminals for said output rows of said second matrix, means connecting a further electrode of each voltage controlled device in said second matrix in common, means connecting the output terminals of said first matrix to said second input conductors, said voltage controlled devices of said second matrix being arrayed in said second matrix to provide at the output terminals of said second matrix signals representative of selected combinations of the terms appearing at the output terminals of said first matrix.

Claim 5

A logic circuit according to claim 2 wherein said input conductors of said first matrix are adapted to supply true input signals and their complements to said first matrix and said at least one output row consists of a number of voltage controlled devices less than half the number of said input signals and their complements.

Claim 6

A metal-insulator-semiconductor integrated circuit comprising a semiconductor substrate, a matrix of input rows and output columns of potential MOS transistors formed on said substrate at each matrix intersection, generally parallel input rows of conductors for respectively receiving substantially simultaneously a plurality of both true logic signals and the complement thereof, each connecting in common the gate electrode of the potential MOS transistors in a respective input row, one of the drain or source electrodes of each potential MOS transistor in an output column being connected in common to form output terminals corresponding to the output columns of said matrix, means connecting the other one of said source or drain electrodes of each of said MOS transistors in common to a reference potential, selected ones of said potential MOS transistors at the intersections of said rows and columns of said matrix having different structural characteristics than the remaining ones of said potential MOS transistors to produce actual transistors only at said selected intersections, said remaining transistors being inoperative, the number of actual transistors in at least one output column of said matrix being less than the number of said input conductors to said matrix for receiving said true input signals, said intersections having actual transistors, the gate electrodes of which are respectively connected to said input conductors, being arrayed in said row and column matrix to provide output signals at said output terminals which are representative of selected combinations of said input signals applied to said input conductors.

Claim 7

A metal-insulator-semiconductor integrated circuit comprising a semiconductor substrate, a matrix of input rows and output columns of potential MOS transistors formed on said substrate at each matrix intersection, generally parallel input rows of conductors for respectively receiving substantially simultaneously a plurality of both true logic signals and the complement thereof, each connecting in common the gate electrode of the potential MOS transistors in a respective input row, one of the drain or source electrodes of each potential MOS transistor in an output column being connected in common to form output terminals corresponding to the output columns of said matrix, means connecting the other one of said source or drain electrodes of each of said MOS transistors in common to a reference potential, selected ones of said potential MOS transistors at the intersections of said rows and columns of said matrix having different structural characteristics than the remaining ones of said potential MOS transistors to produce actual transistors only at said selected intersections, said remaining transistors being inoperative, the number of actual transistors in at least one output column of said matrix being less than the number of said input conductors to said matrix for receiving said true input signals, said intersections having actual transistors, the gate electrodes of which are respectively connected to said input conductors, being arrayed in said row and column matrix to provide output signals at said output terminals which are representative of selected combinations of said input signals applied to said input conductors.

Claim 8

A metal-insulator-semiconductor integrated circuit comprising a semiconductor substrate, a first matrix of input rows and output columns of potential MOS transistors formed on said substrate, generally parallel input rows of conductors each connecting in common the gate electrode of the potential MOS transistors in a respective input row, one of the drain or source electrodes of each potential MOS transitor in an output column being connected in common to form output terminals corresponding to the output columns of said first matrix, means connecting the other one of said source or drain electrodes of each of said MOS transistors in common, selected ones of said potential MOS transistors at the intersections of said rows and columns of said first matrix having different structural characteristics than the remaining ones of said potential MOS transistors to produce actual transistors at said selected intersections and remaining inoperative transistors, said input conductors being adapted to receive at least true input signals for said first matrix, the number of actual transistors in at least one output column of said first matrix being less than the number of true input siGnals and said intersections being selected to provide output signals at said output terminals which are representative of selected combinations of said input signals, and a second matrix of input columns and output rows of voltage controlled devices on said substrate, generally parallel second input conductors connecting the control electrode of each voltage controlled device in an input column of said second matrix in common, another electrode of each voltage controlled device in an output row of said second matrix being connected in common to form output terminals for said output rows of said second matrix, means connecting a further electrode of each voltage controlled device in said second matrix in common, means connecting the output terminals of said first matrix to said second input conductors, said voltage controlled devices of said second matrix being arrayed in said second matrix to provide at the output terminals of said second matrix signals representative of selected combination of the terms appearing at the output terminals of said first matrix.

Claim 9

A metal-insulator-semiconductor integrated circuit comprising a semiconductor substrate, a first matrix of input rows and output columns of potential MOS transistors formed on said substrate, generally parallel input rows of conductors each connecting in common the gate electrode of the potential MOS transistors in a respective input row, one of the drain or source electrodes of each potential MOS transitor in an output column being connected in common to form output terminals corresponding to the output columns of said first matrix, means connecting the other one of said source or drain electrodes of each of said MOS transistors in common, selected ones of said potential MOS transistors at the intersections of said rows and columns of said first matrix having different structural characteristics than the remaining ones of said potential MOS transistors to produce actual transistors at said selected intersections and remaining inoperative transistors, said input conductors being adapted to receive at least true input signals for said first matrix, the number of actual transistors in at least one output column of said first matrix being less than the number of true input siGnals and said intersections being selected to provide output signals at said output terminals which are representative of selected combinations of said input signals, and a second matrix of input columns and output rows of voltage controlled devices on said substrate, generally parallel second input conductors connecting the control electrode of each voltage controlled device in an input column of said second matrix in common, another electrode of each voltage controlled device in an output row of said second matrix being connected in common to form output terminals for said output rows of said second matrix, means connecting a further electrode of each voltage controlled device in said second matrix in common, means connecting the output terminals of said first matrix to said second input conductors, said voltage controlled devices of said second matrix being arrayed in said second matrix to provide at the output terminals of said second matrix signals representative of selected combination of the terms appearing at the output terminals of said first matrix.

Claim 10

A logic circuit according to claim 5 wherein said input conductors are adapted to supply true input signals and their complements to said first matrix and said at least one output column consists of a number of voltage controlled devices less than half the number of said input signals and their complements.

Claim 11

A logic circuit comprising a substrate, a first matrix of input rows and output columns of voltage controlled devices on said substrate, generally parallel input conductors forming input rows to said matrix and connecting in common the control electrode of each voltage controlled device in an input row, another electrode of each voltage control device in each output column being connected in common to form output terminals for said output columns, the number of voltage controlled devices in at least one output column being less than the number of independent input signals to said matrix, said voltage controlled devices in said matrix being arrayed to produce at said output terminals signals representative of selected combinations of said input signals, a second matrix of input columns and output rows of voltage controlled devices on said substrate, generally parallel second input conductors connecting the control electrode of each voltage controlled device in an input column of said second matrix in common, another electrode of eaCh voltage controlled device in an output row of said second matrix being connected in common to form output terminals for said output rows of said second matrix, means connecting a further electrode of each voltage controlled device in said second matrix in common, means connecting the output terminals of said first matrix to said second input conductors, said voltage controlled devices of said second matrix being arrayed in said second matrix to provide at the output terminals of said second matrix signals representative of selected combinations of the terms appearing at the output terminals of said first matrix.

Claim 12

A logic circuit comprising a substrate, a first matrix of input rows and output columns of voltage controlled devices on said substrate, generally parallel input conductors forming input rows to said matrix and connecting in common the control electrode of each voltage controlled device in an input row, another electrode of each voltage control device in each output column being connected in common to form output terminals for said output columns, the number of voltage controlled devices in at least one output column being less than the number of independent input signals to said matrix, said voltage controlled devices in said matrix being arrayed to produce at said output terminals signals representative of selected combinations of said input signals, a second matrix of input columns and output rows of voltage controlled devices on said substrate, generally parallel second input conductors connecting the control electrode of each voltage controlled device in an input column of said second matrix in common, another electrode of eaCh voltage controlled device in an output row of said second matrix being connected in common to form output terminals for said output rows of said second matrix, means connecting a further electrode of each voltage controlled device in said second matrix in common, means connecting the output terminals of said first matrix to said second input conductors, said voltage controlled devices of said second matrix being arrayed in said second matrix to provide at the output terminals of said second matrix signals representative of selected combinations of the terms appearing at the output terminals of said first matrix.

Claim 13

A metal-insulator-semiconductor integrated circuit comprising a semiconductor substrate, a first matrix of input rows and output columns of potential MOS transistors formed on said substrate, generally parallel input rows of conductors each connecting in common the gate electrode of the potential MOS transistors in a respective input row, one of the drain or source electrodes of each potential MOS transistor in an output column being connected in common to form output terminals corresponding to the output columns of said matrix, means connecting the other one of said source or drain electrodes of each of said MOS transistors in common, selected ones of said potential MOS transistors at the intersections of said rows and columns of said matrix having different structural characteristics than the remaining ones of said potential MOS transistors to produce actual transistors at said selected intersections and remaining inoperative transistors, Said input conductors being adapted to receive at least true input signals for said matrix, the number of actual transistors in at least one output column of said matrix being less than the number of true input signals and said intersections being selected to provide output signals at said output terminals which are representative of selected combinations of said input signals, a second matrix of input columns and output rows of voltage controlled devices on said substrate, generally parallel second input conductors connecting the control electrode of each voltage controlled device in an input column of said second matrix in common, another electrode of each voltage controlled device in an output row of said second matrix being connected in common to form output terminals for said output rows of said second matrix, means connecting a further electrode of each voltage controlled device in said second matrix in common, means connecting the output terminals of said first matrix to said second input conductors, said voltage controlled devices of said second matrix being arrayed in said second matrix to provide at the output terminals of said second matrix signals representative of selected combinations of the terms appearing at the output terminals of said first matrix.

Claim 14

A metal-insulator-semiconductor integrated circuit comprising a semiconductor substrate, a first matrix of input rows and output columns of potential MOS transistors formed on said substrate, generally parallel input rows of conductors each connecting in common the gate electrode of the potential MOS transistors in a respective input row, one of the drain or source electrodes of each potential MOS transistor in an output column being connected in common to form output terminals corresponding to the output columns of said matrix, means connecting the other one of said source or drain electrodes of each of said MOS transistors in common, selected ones of said potential MOS transistors at the intersections of said rows and columns of said matrix having different structural characteristics than the remaining ones of said potential MOS transistors to produce actual transistors at said selected intersections and remaining inoperative transistors, Said input conductors being adapted to receive at least true input signals for said matrix, the number of actual transistors in at least one output column of said matrix being less than the number of true input signals and said intersections being selected to provide output signals at said output terminals which are representative of selected combinations of said input signals, a second matrix of input columns and output rows of voltage controlled devices on said substrate, generally parallel second input conductors connecting the control electrode of each voltage controlled device in an input column of said second matrix in common, another electrode of each voltage controlled device in an output row of said second matrix being connected in common to form output terminals for said output rows of said second matrix, means connecting a further electrode of each voltage controlled device in said second matrix in common, means connecting the output terminals of said first matrix to said second input conductors, said voltage controlled devices of said second matrix being arrayed in said second matrix to provide at the output terminals of said second matrix signals representative of selected combinations of the terms appearing at the output terminals of said first matrix.