US4178674A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for forming a contact region between layers of polysilicon with an integral polysilicon resistor
Assignee: Intel Corp
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Filing: 1978-03-27
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Granted: 1979-12-18
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Expires: 1998-03-27
Abstract
Abstract A process for forming an electrical contact region between layers of polysilicon with an integral polysilicon resistor during the fabrication of MOS integrated circuits is disclosed. The contact region which does not require critical alignments, may be formed directly over an active channel or buried (substrate) contact. A silicon nitride mask is formed at the location of the contact region on the first polysilicon layer thereby allowing a thick oxide to be grown on the remainder of the substrate. After removal of the silicon nitride mask, a second polysilicon layer is formed which contacts the first layer at the contact region and defines the resistor. A doping step is used to establish the resistance of the resistor. The process permits the fabrication, by way of example, of a static (bistable) MOS memory cell employing polysilicon loads with an area of approximately 1.5 mils 2 .
Inventors
- 👤 Sheau-Ming S. Liu
- 👤 William H. Owen, III
- 👤 Richard D. Pashley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 07:26
CPC Classifications
H; H10; H10P; H10P95/00; H10P32/00; H10P32/30; H10P32/302; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/063; Y; Y10; Y10S; Y10S257/00; Y10S257/903; Y10S257/904
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
230 words
In the processing of an MOS integrated circuit on a silicon substrate which circuit includes first and second polysilicon layers, an improved process for providing a polysilicon resistor formed from said second polysilicon layer in contact with a selected member formed from said first polysilicon layer, comprising the steps of: forming said first polysilicon layer; forming a silicon nitride layer overlying said first polysilicon layer; defining a plurality of patterns in said silicon nitride layer; etching a plurality of members in said first polysilicon layer corresponding to said patterns; selectively removing said patterns, leaving in place at least a portion of one of said patterns over said selected member; growing an oxide layer on said substrate; removing from said selected member the remaining pattern formed from said silicon nitride layer; forming said second polysilicon layer; doping said second polysilicon layer to obtain a predetermined resistivity; forming a mask over a portion of said second polysilicon layer, said portion corresponding to said polysilicon resistor; again doping said second polysilicon layer such that the doping level under said mask is substantially unchanged; forming at least one line from said second polysilicon layer which includes said portion of said second polysilicon layer corresponding to said polysilicon resistor and which overlies said selected member; whereby a polysilicon resistor formed from said second polysilicon layer contacts said selected member formed from said first polysilicon layer.
Claim 2
Dependent Claim
230 words
In the processing of an MOS integrated circuit on a silicon substrate which circuit includes first and second polysilicon layers, an improved process for providing a polysilicon resistor formed from said second polysilicon layer in contact with a selected member formed from said first polysilicon layer, comprising the steps of: forming said first polysilicon layer; forming a silicon nitride layer overlying said first polysilicon layer; defining a plurality of patterns in said silicon nitride layer; etching a plurality of members in said first polysilicon layer corresponding to said patterns; selectively removing said patterns, leaving in place at least a portion of one of said patterns over said selected member; growing an oxide layer on said substrate; removing from said selected member the remaining pattern formed from said silicon nitride layer; forming said second polysilicon layer; doping said second polysilicon layer to obtain a predetermined resistivity; forming a mask over a portion of said second polysilicon layer, said portion corresponding to said polysilicon resistor; again doping said second polysilicon layer such that the doping level under said mask is substantially unchanged; forming at least one line from said second polysilicon layer which includes said portion of said second polysilicon layer corresponding to said polysilicon resistor and which overlies said selected member; whereby a polysilicon resistor formed from said second polysilicon layer contacts said selected member formed from said first polysilicon layer.
Claim 3
Dependent Claim
18 words
The process defined by claim 1 wherein said selected member is a gate member of a field-effect transistor.
Claim 4
Dependent Claim
13 words
The process defined by claim 2 wherein said doping steps comprise ion implantations.
Claim 5
Dependent Claim
27 words
The process defined by claim 2 wherein a protective oxide layer is formed on said first polysilicon layer prior to the formation of said silicon nitride layer.
Claim 6
Dependent Claim
32 words
The process defined by claim 4 including an etching step to remove said protective oxide layer after said removal from said selected member, said remaining pattern formed from said silicon nitride layer.
Claim 7
Dependent Claim
26 words
The process defined by claim 2 including the formation of a gate oxide layer on said substrate prior to said forming of said first polysilicon layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-12-17 | 1983-06-18 | 1983-12-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-12-17 | 1987-06-18 | 1987-12-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-12-17 | 1991-06-18 | 1991-12-18 | $7700.00 | Window Closed / Lapsed |