Fabrication of integrated circuits containing enhancement-mode FETs and depletion-mode FETs with two layers of polycrystalline silicon utilizing five basic pattern delineating steps

Claim 1

A method for fabricating an array of one-device memory cells and enhancement-mode and depletion-mode FETs on the same semiconductive substrate which comprises: (A) providing a semiconductive substrate of a first conductive type containing active impurities of a first conductive type; (B) providing and delineating predetermined oxide isolation regions above or recessed into the substrate to provide insulating field oxide regions between said memory cell and said enhancement-mode and said depletion-mode FETs and other memory cells and FETs on the same semiconductive substrate; (C) providing an enhancement mode FET gate insulator; (D) depositing and doping a layer of polycrystalline silicon above said gate insulator; (E) then delineating the predetermined polycrystalline silicon gate regions of the enhancement mode FET with an oxidation barrier layer; (F) providing a capacitor insulator and depletion-mode FET gate insulator; (G) thermally diffusing or ion implanting active impurities of a second and opposite conductivity type into predetermined regions of the semiconductive substrate to provide depletion-mode channel regions above which regions are to be subsequently delineated polycrystalline silicon gate regions of depletion-mode FETs; and to provide lower doped silicon electrodes of the storage capacitors above which electrodes are to be subsequently delineated polycrystalline silicon upper electrodes of the storage capacitors of the one-device memory cells; (H) then depositing and doping a second and subsequent layer of polycrystalline silicon above the capacitor insulator, and above said depletion-mode FET gate insulator; (I) then delineating the second and subsequent layer of doped polycrystalline silicon to provide upper electrode regions above the corresponding doped lower silicon electrodes of the storage capacitors, and to provide depletion-mode FET gate regions above corresponding doped depletion-mode channel regions; (J) thermally diffusing or ion implanting active impurities of a second and opposite conductive type into predetermined regions of the semiconductive substrate and at greater doping concentration than the doping concentration employed in step (G) and being sufficient to provide doped sources and drains of both the enhancement-mode FETs and the depletion-mode FETs; (K) thermally growing a silicon dioxide insulating layer over regions of the structure but not over the polycrystalline silicon enhancement-mode FET gate which is still protected by an oxidation barrier layer; (L) removing the oxidation barrier layer from over the enhancement-mode FET gate by use of an etchant; (M) delineating contact holes to polycrystalline silicon upper capacitor electrodes; to doped sources and drains in circuits peripheral to the array of memory cells; and to polycrystalline silicon depletion-mode FET gates; and (N) depositing and delineating a metallic-type high-conductivity electrical interconnection pattern that makes electrical connection to the polycrystalline silicon FET gates, to polycrystalline silicon upper capacitor electrodes, and to source and drain regions.

Claim 2

A method for fabricating an array of one-device memory cells and enhancement-mode and depletion-mode FETs on the same semiconductive substrate which comprises: (A) providing a semiconductive substrate of a first conductive type containing active impurities of a first conductive type; (B) providing and delineating predetermined oxide isolation regions above or recessed into the substrate to provide insulating field oxide regions between said memory cell and said enhancement-mode and said depletion-mode FETs and other memory cells and FETs on the same semiconductive substrate; (C) providing an enhancement mode FET gate insulator; (D) depositing and doping a layer of polycrystalline silicon above said gate insulator; (E) then delineating the predetermined polycrystalline silicon gate regions of the enhancement mode FET with an oxidation barrier layer; (F) providing a capacitor insulator and depletion-mode FET gate insulator; (G) thermally diffusing or ion implanting active impurities of a second and opposite conductivity type into predetermined regions of the semiconductive substrate to provide depletion-mode channel regions above which regions are to be subsequently delineated polycrystalline silicon gate regions of depletion-mode FETs; and to provide lower doped silicon electrodes of the storage capacitors above which electrodes are to be subsequently delineated polycrystalline silicon upper electrodes of the storage capacitors of the one-device memory cells; (H) then depositing and doping a second and subsequent layer of polycrystalline silicon above the capacitor insulator, and above said depletion-mode FET gate insulator; (I) then delineating the second and subsequent layer of doped polycrystalline silicon to provide upper electrode regions above the corresponding doped lower silicon electrodes of the storage capacitors, and to provide depletion-mode FET gate regions above corresponding doped depletion-mode channel regions; (J) thermally diffusing or ion implanting active impurities of a second and opposite conductive type into predetermined regions of the semiconductive substrate and at greater doping concentration than the doping concentration employed in step (G) and being sufficient to provide doped sources and drains of both the enhancement-mode FETs and the depletion-mode FETs; (K) thermally growing a silicon dioxide insulating layer over regions of the structure but not over the polycrystalline silicon enhancement-mode FET gate which is still protected by an oxidation barrier layer; (L) removing the oxidation barrier layer from over the enhancement-mode FET gate by use of an etchant; (M) delineating contact holes to polycrystalline silicon upper capacitor electrodes; to doped sources and drains in circuits peripheral to the array of memory cells; and to polycrystalline silicon depletion-mode FET gates; and (N) depositing and delineating a metallic-type high-conductivity electrical interconnection pattern that makes electrical connection to the polycrystalline silicon FET gates, to polycrystalline silicon upper capacitor electrodes, and to source and drain regions.

Claim 15

A method for fabricating an integrated circuit containing a plurality of enhancement-mode and depletion-mode FETs on the same semiconductive substrate which comprises: (A) providing a semiconductive substrate of a first conductive type containing active impurities of a first conductive type; (B) providing and delineating predetermined oxide isolation regions above or recessed into the substrate to provide insulating field oxide regions between said enhancement-mode and said depletion-mode FETs and between other FETs on the same semiconductive substrate; (C) providing an enhancement mode FET gate insulator;

Claim 16

A method for fabricating an integrated circuit containing a plurality of enhancement-mode and depletion-mode FETs on the same semiconductive substrate which comprises: (A) providing a semiconductive substrate of a first conductive type containing active impurities of a first conductive type; (B) providing and delineating predetermined oxide isolation regions above or recessed into the substrate to provide insulating field oxide regions between said enhancement-mode and said depletion-mode FETs and between other FETs on the same semiconductive substrate; (C) providing an enhancement mode FET gate insulator;