MISFET and method of manufacture

Claim 2

A metal-insulator-semiconductor field-effect transistor means comprising: a body of semiconductive material of a first conductivity type having formed therein a pair of spaced apart regions of a second conductivity type respectively forming the source and drain of said transistor means; a belt-like region of said first conductivity type circumscribing said source and drain regions, said belt-like region having a higher impurity concentration than said body of semiconductive material; an external region of said second conductivity type disposed outside said belt-like region and contiguous therewith so as to form a P-N junction therebetween; and metallic gate electrode means disposed above and electrically insulated from the region separating said source and drain regions and extending across said P-N junction, said gate electrode ohmically contacting said external region, said P-N junction providing a gate breakdown protection means for said transistor means.

Claim 3

A metal-insulator-semiconductor field-effect transistor means as recited in claim 1 and further including a second external region of said second conductivity type disposed outside of and contiguous with said belt-like region and forming a second P-N junction therebetween and metallic interconnect means ohmically contacting said second external region and said belt-like region across said second P-N junction and forming a topside contact to said body of semiconductive material.

Claim 4

A metal-insulator-semiconductor field-effect transistor means as recited in claim 2 wherein said first conductivity type is of an N-type impurity and said second conductivity type is of P-type impurity.

Claim 5

A metal-insulator-semiconductor field-effect transistor means as recited in claim 2 wherein said source and drain regions are formed by diffusing highly concentrated antimony into a P-type substrate.

Claim 6

A metal-insulator-semiconductor field-effect transistor means comprising: a first region forming the source and a second region spaced from said first region forming the drain, said first and second regions being of a first conductivity type and being diffused into a body of semiconductive material of the opposite conductivity type; metallic gate means disposed above the region separating said first and second regions and being separated therefrom by a layer of electrical insulating material; an elongated third region of said opposite conductivity type separating said first and second regions from any adjacent regions of the same conductivity type which are interconnected with either of said first or second regions, said third region having a higher impurity concentration than said body of semiconductive material; a fourth region of said first conductivity type disposed contiguous with said third region and forming a P-N junction therebetween; and a metallic interconnect means alloyed across the junction of said third region and said fourth region forming a good ohmic topside contact to said body of semiconductive material.

Claim 7

A metal-insulator-semiconductor field-effect transistor means comprising: a first region forming the source and a second region spaced from said first region forming the drain, said first and second regions being of a first conductivity type and being diffused into a body of semiconductive material of the opposite conductivity type; metallic gate means disposed above the region separating said first and second regions and being separated therefrom by a layer of electrical insulating material; an elongated third region of said opposite conductivity type separating said first and second regions from any adjacent regions of the same conductivity type which are interconnected with either of said first or second regions, said third region having a higher impurity concentration than said body of semiconductive material; a fourth region of said first conductivity type disposed contiguous with said third region and forming a P-N junction therebetween; and a metallic interconnect means alloyed across the junction of said third region and said fourth region forming a good ohmic topside contact to said body of semiconductive material.

Claim 8

A metal-insulator-semiconductor field-effect transistor means as recited in claim 5 wherein a fifth region of said first conductivity type is provided contiguous with said third region forming a P-N junction therebetween, said fifth region being disposed on the side of said third region opposite said first and second regions, said gate means being ohmically connected to said fifth region so as to provide a gate breakdown protection means for said transistor means.

Claim 9

A metal-insulator-semiconductor field-effect transistor means as recited in claim 6 wherein said third region forms an inversion barrier encircling said first and second regions.

Claim 10

A metal-insulator-semiconductor field-effect transistor means as recited in claim 7 wherein said first and second regions are formed by diffusing highly concentrated antimony with a P-type substrate.