Method for fabricating FET one-device memory cells with two layers of polycrystalline silicon and fabrication of integrated circuits containing arrays of the memory cells charge storage capacitors utilizing five basic pattern deliberating steps

Claim 1

A method for fabricating an integrated circuit array of FET one-device memory cells having oxide isolation between cells, and each cell of the array having a doped bit line; polysilicon-gate FET self-aligned to source and drain regions; a metallic-type high-electrically conductive word line; a self-registering connection between the gate and the word line; and a charge storge capacitor with a polysilicon upper electrode and a doped silicon lower electrode beneath the polysilicon upper electrode, the lower electrode being doped opposite in conductivity type to the substrate doping, which comprises: (A) providing a semiconductive substrate of a first conductive type containing active impurities of a first conductive type; (B) providing and delineating predetermined oxide isolation regions above or recessed into the substrate to provide insulating field oxide regions between memory cells of the array; (C) providing an insulator for the FET gates; (D) depositing a layer of polycrystalline silicon above the gate insulator; (E) then delineating the layer of polycrystalline silicon employing an oxidation barrier layer to provide the predetermined polycrystalline silicon gate regions of the FETs; (F) thermally diffusing or ion implanting active impurities of a second and opposite conductive type into preselected regions of the semiconductive substrate to provide doped bit lines (FET drains); connection regions (FET sources); and lower silicon electrodes of the storage capacitors, above which electrodes, are to be subsequently delineated polycrystalline silicon upper electrodes of the storage capacitors; (G) providing an insulator for the storage capacitors; (H) then depositing a second and subsequent layer of polycrystalline silicon above the insulator for the storage capacitors; (I) then delineating the second and subsequent layer of doped polycrystalline silicon to provide predetermined upper electrode regions above the corresponding doped lower silicon electrodes or the storage capacitors; (J) thermally growing a silicon dioxide insulating layer over regions of the structure but not over the polycrystalline silicon FET gates which are still protected by an oxidation barrier layer; (K) removing the oxidation barrier layer from over the FET gates by use of an etchant; (L) delineating contact holes to polycrystalline silicon upper capacitor electrodes; and to doped sources and drains in circuits peripheral to the array of memory cells; (M) depositing and delineating a metallic-type high-conductivity electrical interconnection pattern that makes electrical connection to the polycrystalline silicon FET gates in the array of memory cells; to polycrystalline silicon upper capacitor electrodes; and to FET gates, sources, and drains in circuits peripheral to the array of memory cells.

Claim 2

A method for fabricating an integrated circuit array of FET one-device memory cells having oxide isolation between cells, and each cell of the array having a doped bit line; polysilicon-gate FET self-aligned to source and drain regions; a metallic-type high-electrically conductive word line; a self-registering connection between the gate and the word line; and a charge storge capacitor with a polysilicon upper electrode and a doped silicon lower electrode beneath the polysilicon upper electrode, the lower electrode being doped opposite in conductivity type to the substrate doping, which comprises: (A) providing a semiconductive substrate of a first conductive type containing active impurities of a first conductive type; (B) providing and delineating predetermined oxide isolation regions above or recessed into the substrate to provide insulating field oxide regions between memory cells of the array; (C) providing an insulator for the FET gates; (D) depositing a layer of polycrystalline silicon above the gate insulator; (E) then delineating the layer of polycrystalline silicon employing an oxidation barrier layer to provide the predetermined polycrystalline silicon gate regions of the FETs; (F) thermally diffusing or ion implanting active impurities of a second and opposite conductive type into preselected regions of the semiconductive substrate to provide doped bit lines (FET drains); connection regions (FET sources); and lower silicon electrodes of the storage capacitors, above which electrodes, are to be subsequently delineated polycrystalline silicon upper electrodes of the storage capacitors; (G) providing an insulator for the storage capacitors; (H) then depositing a second and subsequent layer of polycrystalline silicon above the insulator for the storage capacitors; (I) then delineating the second and subsequent layer of doped polycrystalline silicon to provide predetermined upper electrode regions above the corresponding doped lower silicon electrodes or the storage capacitors; (J) thermally growing a silicon dioxide insulating layer over regions of the structure but not over the polycrystalline silicon FET gates which are still protected by an oxidation barrier layer; (K) removing the oxidation barrier layer from over the FET gates by use of an etchant; (L) delineating contact holes to polycrystalline silicon upper capacitor electrodes; and to doped sources and drains in circuits peripheral to the array of memory cells; (M) depositing and delineating a metallic-type high-conductivity electrical interconnection pattern that makes electrical connection to the polycrystalline silicon FET gates in the array of memory cells; to polycrystalline silicon upper capacitor electrodes; and to FET gates, sources, and drains in circuits peripheral to the array of memory cells.