Non-volatile, electrically erasable and reprogrammable memory element

Claim 2

A non-volatile, electrically erasable and reprogrammable memory element comprising a single p-channel MOS transistor with a polycrystalline silicon floating gate capacitively coupled to a control electrode, wherein, said polycrystalline silicon floating gate is arranged, at least over a portion of the channel region, on a thin injection-type oxide and, outside the channel region, on a field oxide layer which is substantially thicker; said control electrode covers said floating gate and is separated from said floating gate by at least one gate oxide layer which is substantially thicker than said injection-type oxide; and the thickness of said injection-type oxide and said gate oxide is chosen so that said floating gate can be negatively charged by avalanche of the drain-substrate junction and can be discharged by field emission of electrons from said floating gate towards the substrate by applying a negative voltage to said control electrode.

Claim 3

A non-volatile electrically erasable and reprogrammable memory element comprising a single p-channel MOS transistor with a polycrystalline silicon floating gate capacitively coupled to a control electrode, wherein, said polycrystalline silicon floating gate is arranged, at least over a portion of the channel region, on a thin injection-type oxide and, outside the channel region, on a field oxide which is substantially thicker; said control electrode covers said floating gate and the channel region not covered by the floating gate, said control electrode being separated from said floating gate and from said channel region not covered by the floating gate, by at least one gate oxide layer which is substantially thicker than the said injection-type oxide; and the thickness of said injection-type oxide and said gate oxide is chosen so that said floating gate can be negatively charged by avalanche of the drain-substrate junction and can be discharged by field emission of electrons from said floating gate towards the substrate by applying a negative voltage to the said control electrode.

Claim 4

A non-volatile electrically erasable and reprogrammable memory element comprising a single p-channel MOS transistor with a polycrystalline silicon floating gate capacitively coupled to a control electrode, wherein, said polycrystalline silicon floating gate is arranged, at least over a portion of the channel region, on a thin injection-type oxide and, outside the channel region, on a field oxide which is substantially thicker; said control electrode covers said floating gate and the channel region not covered by the floating gate, said control electrode being separated from said floating gate and from said channel region not covered by the floating gate, by at least one gate oxide layer which is substantially thicker than the said injection-type oxide; and the thickness of said injection-type oxide and said gate oxide is chosen so that said floating gate can be negatively charged by avalanche of the drain-substrate junction and can be discharged by field emission of electrons from said floating gate towards the substrate by applying a negative voltage to the said control electrode.

Claim 5

A memory element as claimed in claim 1 or claim 2 wherein said floating gate is arranged on said injection oxide in a first zone of the channel region situated on the drain side and in at least a second zone of said channel region, and wherein it is arranged on the field oxide in the other zones.

Claim 6

A memory element as claimed in claim 3 wherein said second channel region is situated on the source side.

Claim 7

A memory element as claimed in any preceding claim wherein the source region is produced by a p-doped well formed in the substrate.

Claim 8

A memory element as claimed in claim 1 or 2 wherein said floating gate is at least partially doped with an n-type dopant.

Claim 9

A memory element as claimed in claim 1 or 2 wherein said control electrode is produced from aluminum.

Claim 10

A memory element as claimed in claim 1 or 2 wherein said control electrode is produced from polycrystalline silicon.

Claim 11

A memory element as claimed in 2 wherein said floating gate only covers the channel region partially and on the drain side, and is separated therefrom by an injection-type oxide layer.

Claim 12

A memory element as claimed in claim 9 wherein said control electrode is made of polycrystalline silicon.

Claim 13

A memory element as claimed in claim 10 wherein said floating gate is doped with an n-type dopant and said control electrode is doped with a p-type dopant.

Claim 14

A memory element as claimed in any of claims 9 to 11 wherein said injection-type oxide is about 200 A thick and said gate oxide is about 1,000 A thick.

Claim 15

An integrated circuit comprising a plurality of memory elements as claimed in claim 1 arranged in matrix form, the circuit also comprising means for the supply and control of said memory elements, wherein said circuit is supplied from a single external voltage source and wherein said means for supply and control comprise an oscillator emitting high frequency pulses, a voltage multiplier supplying from the said oscillator pulses voltages having a value which is higher than that of said external voltage source, and selection circuits capable of applying, in response to external control signals, said voltages supplied by the multiplier to the electrodes of said memory element so as to write, erase or read them.