US5053841A
Expired / Lapsed
US
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Nonvolatile semiconductor memory
Assignee: Toshiba Corp
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Filing: 1989-10-18
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Granted: 1991-10-01
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Expires: 2009-10-18
Abstract
Abstract A nonvolatile semiconductor memory includes a cell array in which electrically erasable programmable nonvolatile semiconductor memory cells, each using a cell transistor having source and drain regions in a semiconductor substrate, and a gate electrode with a three-layered structure on the semiconductor substrate are arranged in a matrix form. In the gate electrode having the three-layered structure, a first-layer floating gate electrode opposes a semiconductor substrate surface through a first gate insulating film, and a second- or third-layer gate electrode serves as one of erase and control gate electrodes. The erase gate electrode opposes a part of the floating gate electrode through a tunnel insulating film, and the control gate electrode opposes the floating gate electrode through a second gate insulating film. The erase and control gate electrodes are arranged to be parallel to each other, and to be perpendicular to the source and drain regions. Of two cell transistors adjacent to each other in a length direction of the channel region, the source region of one cell transistor is common to the drain region of the other cell transistor, and the cell transistors adjacent to each other in the widthwise direction of the channel region are element-isolated by an element isolation region formed in the semiconductor substrate between the channel regions.
Inventors
- 👤 Tadashi Miyakawa
- 👤 Masamichi Asano
- 👤 Tadayuki Taura
- 👤 Atsushi Shoji
- 👤 Michiharu Inami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:28
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/686
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
227 words
A nonvolatile semiconductor memory comprising: a cell array in which electrically erasable programmable nonvolatile semiconductor memory cells, each using a cell transistor including source and drain regions in a semiconductor substrate, a channel region between said source and drain regions, and a gate electrode having a three-layered structure on said semiconductor substrate, are arranged in a matrix form; said gate electrode having the three-layered structure, comprising a first-layer floating gate electrode which opposes a semiconductor substrate surface through a first gate insulating film, and second- and third-layer gate electrodes each of which serves as one of erase and control gate electrodes, said erase gate electrode opposing a part of said floating gate electrode through a tunnel insulating film, and said control gate electrode opposing said floating gate electrode through a second gate insulating film; said erase and control gate electrodes arranged parallel to each other in a row direction and perpendicular to said source and drain regions arranged in a column direction array; and said cell transistors arranged adjacent to each other in the row direction through the channel region such that the source region of one of the adjacent transistors is shared by the drain region of the other transistor to provide a common source/drain region, the adjacent cell transistors being isolated by an element isolation region formed in the semiconductor substrate between the channel regions.
Claim 2
Dependent Claim
227 words
A nonvolatile semiconductor memory comprising: a cell array in which electrically erasable programmable nonvolatile semiconductor memory cells, each using a cell transistor including source and drain regions in a semiconductor substrate, a channel region between said source and drain regions, and a gate electrode having a three-layered structure on said semiconductor substrate, are arranged in a matrix form; said gate electrode having the three-layered structure, comprising a first-layer floating gate electrode which opposes a semiconductor substrate surface through a first gate insulating film, and second- and third-layer gate electrodes each of which serves as one of erase and control gate electrodes, said erase gate electrode opposing a part of said floating gate electrode through a tunnel insulating film, and said control gate electrode opposing said floating gate electrode through a second gate insulating film; said erase and control gate electrodes arranged parallel to each other in a row direction and perpendicular to said source and drain regions arranged in a column direction array; and said cell transistors arranged adjacent to each other in the row direction through the channel region such that the source region of one of the adjacent transistors is shared by the drain region of the other transistor to provide a common source/drain region, the adjacent cell transistors being isolated by an element isolation region formed in the semiconductor substrate between the channel regions.
Claim 3
Dependent Claim
50 words
A memory according to claim 1, wherein said second-layer gate electrode is shifted in the column direction with respect to said first-layer floating gate electrode, and an insulating film having a high breakdown voltage is buried between said second-layer gate electrode and said element isolation region on said semiconductor substrate.
Claim 4
Dependent Claim
72 words
A memory according to claim 2, wherein said floating gate electrode is shorter than the channel length of said channel region, and has an offset portion having no floating gate electrode portion on said channel region and near said source or drain region, said offset portion having a selection transistor portion in which said control gate electrode is formed to oppose a part of said channel region through a gate insulating film.
Claim 5
Dependent Claim
73 words
A memory according to claim 1, wherein said cell array is arranged such that common column source/drain regions, in which common row source and drain regions in cell transistors adjacent to each other are formed, are formed in memory cells in the column direction, common row erase gate electrodes of memory cells are formed in the row direction, and common row control gate electrodes of memory cells are formed in the row direction.
Claim 6
Dependent Claim
30 words
A memory according to claim 4, wherein each of said erase gate electrodes is formed to be common to cell transistors in at least two rows adjacent to each other.
Claim 7
Dependent Claim
98 words
A memory according to claim 1, wherein said cell array has a plurality of groups, each group including common row erase gate electrodes and an erase voltage is applied to said erase gate electrodes in one of three methods, in the first of which the erase voltage is applied to at least one selected electrode of each row, in the second of which the erase voltage is simultaneously applied to all electrodes of every row in every group, and in the third of which the erase voltage is applied to the rows of electrodes in any selected group.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-30 | 1995-04-01 | 1995-10-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-30 | 1999-04-01 | 1999-10-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-30 | 2003-04-01 | 2003-10-01 | $7700.00 | Window Closed / Lapsed |