US6504207B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method to create EEPROM memory structures integrated with high performance logic and NVRAM, and operating conditions for the same
Assignee: International Business Machines Corp
•
Filing: 2000-06-30
•
Granted: 2003-01-07
•
Expires: 2020-06-30
Abstract
Abstract A method and structure for a EEPROM memory device integrated with high performance logic or NVRAM. The EEPROM device includes a floating gate and program gate self-aligned with one another. During programming, electron tunneling occurs between the floating gate and the program gate.
Inventors
- 👤 Bomy A. Chen
- 👤 Jay G. Harrington
- 👤 Kevin M. Houlihan
- 👤 Dennis Hoyniak
- 👤 Chung Hon Lam
- 👤 Hyun Koo Lee
- 👤 Rebecca D. Mih
- 👤 Jed H. Rankin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:01
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/6891; H10D30/6892; H10D64/00; H10D64/01; H10D64/031; H10D64/035; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
103 words
A memory device formed on a silicon substrate, comprising: a floating gate; a program gate; a first select device and a second select device, said first select device and said second select device both being self-aligned to said floating gate and said program gate; and first and second substantially vertical dielectric spacers interposed between said program gate and said first select device and said second select device, respectively, but not between said floating gate and said first select device and said second select device, wherein said first select device and said second select device comprise a first wordline and a second wordline, respectively.
Claim 2
Dependent Claim
103 words
A memory device formed on a silicon substrate, comprising: a floating gate; a program gate; a first select device and a second select device, said first select device and said second select device both being self-aligned to said floating gate and said program gate; and first and second substantially vertical dielectric spacers interposed between said program gate and said first select device and said second select device, respectively, but not between said floating gate and said first select device and said second select device, wherein said first select device and said second select device comprise a first wordline and a second wordline, respectively.
Claim 3
Dependent Claim
18 words
A memory device of claim 1 , wherein said program gate comprises polysilicon formed between silicon-rich oxide layers.
Claim 4
Dependent Claim
39 words
A memory device of claim 1 further comprising a dielectric layer interposed between said floating gate and said program gate, said dielectric layer adapted to enhance tunneling of electrons between said floating gate and said program gate during programming.
Claim 5
Dependent Claim
28 words
A memory device of claim 3 wherein said dielectric layer is further adapted to enhance tunneling of electrons between said floating gate and said program gate during erasing.
Claim 6
Dependent Claim
13 words
A memory device of claim 3 wherein said dielectric layer comprises silicon-rich oxide.
Claim 7
Dependent Claim
18 words
A memory device of claim 3 wherein said dielectric layer further comprises a layer of stoichiometric silicon dioxide.
Claim 8
Dependent Claim
23 words
A memory device of claim 6 wherein said dielectric layer comprises a layer of stoichiometric silicon dioxide between two layers of silicon-rich oxide.
Claim 9
Dependent Claim
19 words
A memory device of claim 7 wherein said layer of stoichiometric silicon dioxide has thickness of about 60 Å.
Claim 10
Dependent Claim
22 words
A memory device of claim 8 wherein at least one of said layers of silicon-rich oxide has thickness of about 60 Å.
Claim 11
Dependent Claim
20 words
A memory device of claim 9 wherein both of said layers of silicon-rich oxide have thickness of about 60 Å.
References Cited (Backward Citations)
US5091882A
Cited
US5380672A
Cited
US5212541A
Cited
US5284784A
Cited
US5614747A
Cited
US6157058A
Cited
US6271091B1
Cited
US5918124A
Cited
US5986941A
Cited
US6426257B1
Cited
US5991204A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-01-06 | 2006-07-08 | 2007-01-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-01-06 | 2010-07-08 | 2011-01-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-01-06 | 2014-07-08 | 2015-01-07 | $7700.00 | Window Closed / Lapsed |