Dense vertical programmable read only memory cell structures and processes for making them

Claim 1

A method of forming an electrically programmable memory device on a semiconductor substrate, comprising the steps of: forming source and drain regions within the substrate at one surface thereof, depositing a layer of isolation dielectric to a thickness on said substrate surface, said substrate surface being characterized by being substantially planar at least between the source and drain regions, removing portions of the isolation dielectric layer to form a trench that exposes the substantially planar substrate surface along a length thereof between said source and drain regions, said trench having a cross-sectional shape in a direction orthogonal to the substrate surface with a depth equal to said dielectric layer thickness and at least a segment of the depth adjacent the substrate surface being rectangularly shaped with a width between sidewalls thereof that is equal to or less than two times said isolation dielectric layer thickness, said removing step being accomplished without removing any substantial amount of the substrate within the trench, forming a gate dielectric layer on the exposed substrate surface within said trench, forming an electrically conductive floating gate over said gate dielectric and within said trench, forming a control gate dielectric layer over said floating gate, and forming an electrically conductive control gate over said floating gate, whereby said floating and control gates are capacitively coupled between opposing surface areas thereof which are separated by said control gate dielectric layer.

Claim 2

A method of forming an electrically programmable memory device on a semiconductor substrate, comprising the steps of: forming source and drain regions within the substrate at one surface thereof, depositing a layer of isolation dielectric to a thickness on said substrate surface, said substrate surface being characterized by being substantially planar at least between the source and drain regions, removing portions of the isolation dielectric layer to form a trench that exposes the substantially planar substrate surface along a length thereof between said source and drain regions, said trench having a cross-sectional shape in a direction orthogonal to the substrate surface with a depth equal to said dielectric layer thickness and at least a segment of the depth adjacent the substrate surface being rectangularly shaped with a width between sidewalls thereof that is equal to or less than two times said isolation dielectric layer thickness, said removing step being accomplished without removing any substantial amount of the substrate within the trench, forming a gate dielectric layer on the exposed substrate surface within said trench, forming an electrically conductive floating gate over said gate dielectric and within said trench, forming a control gate dielectric layer over said floating gate, and forming an electrically conductive control gate over said floating gate, whereby said floating and control gates are capacitively coupled between opposing surface areas thereof which are separated by said control gate dielectric layer.

Claim 16

A method of forming a two dimensional array of electrically programmable memory devices on a semiconductor substrate, comprising the steps of: forming in one substantially planar surface of the substrate a plurality of elongated parallel source and drain regions with their lengths extending in one direction across the substrate and spaced apart in a second direction across said substrate, said first and second directions being substantially perpendicular to each other, depositing a substantially uniform thickness layer of isolation dielectric directly on said semiconductor substrate, forming in said isolation dielectric layer a plurality of elongated parallel trenches extending through said layer to said substantially planar substrate surface in a manner that they have a substantially rectangular cross-sectional shape in at least a segment adjacent the substrate surface that is a portion of their depth and with a width in said segment that is equal to or less than two times their depth, said trenches having their lengths extending in said second direction and being spaced apart in said first direction, growing a gate dielectric on the substrate surface within said trenches, depositing a first electrically conductive layer over said isolation dielectric and within the trenches in a manner that grooves are left along the length of the trenches, removing portions of said first electrically conductive layer to leave a plurality of floating gates spaced along the length of the trenches, said floating gates extending at least part of the distance between adjacent source and drain diffusion regions, the floating gates of one trench being separated from those of other trenches, forming a layer of control gate oxide on said floating gates, depositing a second electrically conductive layer over the structure in a manner to substantially fill the floating gate grooves and trenches, removing portions of said second electrically conductive layer to leave a plurality of elongated parallel control gates extending along the trenches.

Claim 17

A method of forming a two dimensional array of electrically programmable memory devices on a semiconductor substrate, comprising the steps of: forming in one substantially planar surface of the substrate a plurality of elongated parallel source and drain regions with their lengths extending in one direction across the substrate and spaced apart in a second direction across said substrate, said first and second directions being substantially perpendicular to each other, depositing a substantially uniform thickness layer of isolation dielectric directly on said semiconductor substrate, forming in said isolation dielectric layer a plurality of elongated parallel trenches extending through said layer to said substantially planar substrate surface in a manner that they have a substantially rectangular cross-sectional shape in at least a segment adjacent the substrate surface that is a portion of their depth and with a width in said segment that is equal to or less than two times their depth, said trenches having their lengths extending in said second direction and being spaced apart in said first direction, growing a gate dielectric on the substrate surface within said trenches, depositing a first electrically conductive layer over said isolation dielectric and within the trenches in a manner that grooves are left along the length of the trenches, removing portions of said first electrically conductive layer to leave a plurality of floating gates spaced along the length of the trenches, said floating gates extending at least part of the distance between adjacent source and drain diffusion regions, the floating gates of one trench being separated from those of other trenches, forming a layer of control gate oxide on said floating gates, depositing a second electrically conductive layer over the structure in a manner to substantially fill the floating gate grooves and trenches, removing portions of said second electrically conductive layer to leave a plurality of elongated parallel control gates extending along the trenches.

Claim 18

A method of forming a two dimensional array of electrically programmable memory devices on a semiconductor substrate, comprising the steps of: forming in one substantially planar surface of the substrate a plurality of elongated parallel source and drain regions with their lengths extending in one direction across the substrate and spaced apart in a second direction across said substrate, said first and second directions being substantially perpendicular to each other, depositing a predetermined substantially uniform thickness layer of isolation dielectric in a manner that it is carried by the substrate, forming in said isolation dielectric layer a plurality of elongated parallel trenches extending through said layer to said substantially planar substrate surface in a manner that they have a substantially rectangular cross-sectional shape in at least a segment adjacent the substrate surface that is a significant portion of their depth and with a width in said segment that is equal to or less than two times their depth, said trenches having their lengths extending in said second direction and being spaced apart in said first direction, growing a gate dielectric on the substrate surface within said trenches, depositing a first electrically conductive layer over said isolation dielectric and within the trenches in a manner to fill said trenches, removing portions of said first electrically conductive layer to leave a plurality of floating gates spaced along the length of the trenches and having ends within the trench that are oriented substantially orthogonal to said substrate surface, said floating gates extending at least part of the distance between adjacent source and drain diffusion regions, the floating gates of one trench being separated from those of other trenches, forming a layer of control gate oxide over said floating gates, depositing a second electrically conductive layer over the structure in a manner to cover the floating gates and substantially fill the trenches, removing portions of said second electrically conductive layer to leave a plurality of elongated parallel control gates extending along the trenches.

Claim 19

A method of forming a two dimensional array of electrically programmable memory devices on a semiconductor substrate, comprising the steps of: forming in one substantially planar surface of the substrate a plurality of elongated parallel source and drain regions with their lengths extending in one direction across the substrate and spaced apart in a second direction across said substrate, said first and second directions being substantially perpendicular to each other, depositing a predetermined substantially uniform thickness layer of isolation dielectric in a manner that it is carried by the substrate, forming in said isolation dielectric layer a plurality of elongated parallel trenches extending through said layer to said substantially planar substrate surface in a manner that they have a substantially rectangular cross-sectional shape in at least a segment adjacent the substrate surface that is a significant portion of their depth and with a width in said segment that is equal to or less than two times their depth, said trenches having their lengths extending in said second direction and being spaced apart in said first direction, growing a gate dielectric on the substrate surface within said trenches, depositing a first electrically conductive layer over said isolation dielectric and within the trenches in a manner to fill said trenches, removing portions of said first electrically conductive layer to leave a plurality of floating gates spaced along the length of the trenches and having ends within the trench that are oriented substantially orthogonal to said substrate surface, said floating gates extending at least part of the distance between adjacent source and drain diffusion regions, the floating gates of one trench being separated from those of other trenches, forming a layer of control gate oxide over said floating gates, depositing a second electrically conductive layer over the structure in a manner to cover the floating gates and substantially fill the trenches, removing portions of said second electrically conductive layer to leave a plurality of elongated parallel control gates extending along the trenches.

Claim 20

The method according to either of claims 15 or 16 wherein the step of forming the trenches includes the step of forming spacers along the trench sidewalls to alter their cross-sectional shape to narrow a distance between opposing trench sidewalls adjacent the substrate surface.

Claim 21

The method according to either of claims 15 or 16 wherein the step of forming the trenches includes the step of forming such trenches with a width adjacent the substrate surface that is equal to or less than their depth.

Claim 22

The method according to either of claims 15 or 16 which additionally comprises the step, prior to the step of depositing the isolation dielectric layer, of forming a third electrically conductive layer insulated from the substrate, and wherein the step of forming the isolation dielectric layer includes depositing said isolation dielectric layer on said third conductive layer and the step of forming the trenches includes removal of the third conductive layer from regions of the trenches, thereby to leave a plurality of elongated erase gates with their lengths extending in said second direction and positioned between the trenches with opposite side surfaces abutting walls of adjacent trenches.

Claim 23

The method according to either of claims 15 or 16 which additionally comprises the step, prior to the step of forming trenches in the isolation dielectric layer, of forming a third electrically conductive layer over the isolation dielectric, and wherein the step of forming the trenches includes removal of the third conductive layer from regions of the trenches, thereby to leave a plurality of elongated erase gates with their lengths extending in said second direction and positioned between the trenches with opposite side surfaces abutting walls of adjacent trenches.

Claim 24

The method according to either of claims 15 or 16 which additionally comprises the step, prior to the step of forming trenches in the isolation dielectric layer, of forming a third electrically conductive layer insulated from the substrate, and wherein the step of forming the trenches includes removal of the third conductive layer from regions of the trenches, thereby to leave a plurality of elongated erase gates with their lengths extending in said second direction and positioned between the trenches with opposite side surfaces abutting walls of adjacent trenches, said method additionally including the steps, prior to the step of depositing the first conductive layer, of exposing the erase gate sidewalls into their abutting trenches and growing only one oxide layer thereon, thereby forming an erase gate dielectric.

Claim 25

The method according to either of claims 15 or 16 which additionally comprises the step, prior to the step of forming trenches in the isolation dielectric layer, of forming a third electrically conductive layer insulated from the substrate, and wherein the step of forming the trenches includes removal of the third conductive layer from regions of the trenches, thereby to leave a plurality of elongated erase gates with their lengths extending in said second direction and positioned between the trenches with opposite side surfaces abutting walls of adjacent trenches, said method additionally including the steps, prior to the step of depositing the first conductive layer, of exposing the erase gate sidewalls into their abutting trenches and growing only one oxide layer, thereby forming an erase gate dielectric, and further wherein the step of depositing the first conductive layer includes the step of depositing in-situ doped polysilicon.

Claim 26

The method according to either of claims 15 or 16 wherein the step of forming the trenches includes a single anisotropic etching step.

Claim 27

The method according to either of claims 15 or 16 wherein the step of forming the trenches includes the steps of removing an initial portion of the isolation dielectric by an isotropic etch through a mask opening until a portion of the isolation dielectric layer is removed, and thereafter removing a remaining portion of the isolation dielectric layer by an anisotropic etch through said mask opening.