Memory cell structure of semiconductor memory device

Claim 1

A memory cell employed in an erasable programmable read-only memory, comprising: a semiconductor substrate having a surface; a source region formed on the substrate; a channel region formed on the source region; a drain region formed on the channel region; a trench penetrating the drain region and the channel region, reaching the source region, and extending in a direction substantially perpendicular to the surface of the substrate the trench including an inner surface; a floating gate comprising a first gate insulating layer formed on the inner surface of the trench, including an inner surface, and a first conductor formed in partial contact with the inside surface of the first gate insulating layer, and including a portion not in contact with the first gate insulating layer; and a control gate comprising a second gate insulating layer formed on the portion of the first conductor which is not in contact with the first gate insulating layer, and a second conductor formed on the second gate insulating layer opposite to the portion in contact with the first conductor; wherein a portion of the floating gate and a portion of the control gate project perpendicularly from the surface of the semiconductor substrate.