US4996572A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1989-12-11
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Granted: 1991-02-26
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Expires: 2009-12-11
Abstract
Abstract A semiconductor memory device containing a number of memory cells each having a floating gate, an erase gate, and a control gate. In a data erasure mode, electrons are discharged from the floating gate into the erase gate electrode. An insulating film interlaid between the erase gate and the control gate has a three-layered structure consisting of a silicon oxide film, a silicon nitride film, and a silicon oxide film.
Inventors
- 👤 Shinichi Tanaka
- 👤 Masayuki Hori
- 👤 Noriyoshi Tozawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 01:07
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0135; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
210 words
A semiconductor memory device comprising: a first conductive semiconductor substrate; a floating gate formed on the semiconductor substrate with a first insulating film inserted between said first conductive semiconductor substrate and said floating gate, said floating gate being made of polycrystal silicon which includes an impurity at a density of less than 6×10 20 /cm 3 ; a silicon oxide film formed on said floating gate and having a number of irregularities on its top surface; an erase gate formed on the first insulating film and formed on part of said silicon oxide film so as to overlap part of the floating gate, said erase gate being made of polycrystal silicon which includes an impurity at a density of at least 6×10 20 /cm 3 ; a second insulating film formed on the silicon oxide film over the floating gate and the erase gate, said second insulating film comprising a three-layered structure made of a first silicon oxide film, a silicon nitride film and a second silicon oxide film; and a control gate formed on the second insulating film, over the floating gate and the erase gate, said control gate being made of polycrystal silicon which includes an impurity at a density of at least 6×10 20 /cm 3 .
Claim 2
Dependent Claim
210 words
A semiconductor memory device comprising: a first conductive semiconductor substrate; a floating gate formed on the semiconductor substrate with a first insulating film inserted between said first conductive semiconductor substrate and said floating gate, said floating gate being made of polycrystal silicon which includes an impurity at a density of less than 6×10 20 /cm 3 ; a silicon oxide film formed on said floating gate and having a number of irregularities on its top surface; an erase gate formed on the first insulating film and formed on part of said silicon oxide film so as to overlap part of the floating gate, said erase gate being made of polycrystal silicon which includes an impurity at a density of at least 6×10 20 /cm 3 ; a second insulating film formed on the silicon oxide film over the floating gate and the erase gate, said second insulating film comprising a three-layered structure made of a first silicon oxide film, a silicon nitride film and a second silicon oxide film; and a control gate formed on the second insulating film, over the floating gate and the erase gate, said control gate being made of polycrystal silicon which includes an impurity at a density of at least 6×10 20 /cm 3 .
Claim 3
Dependent Claim
18 words
A semiconductor memory device according to claim 1, wherein said first conductive semiconductor substrate comprises a silicon substrate.
Claim 4
Dependent Claim
35 words
A semiconductor memory device according to claim 1, wherein said first silicon oxide film is ≧400 Angstroms in thickness, said silicon nitride film is ≧50 Angstroms, and said second silicon oxide film is ≧50 Angstroms.
Claim 5
Dependent Claim
49 words
A semiconductor memory device according to claim 1, wherein the impurity densities of the impurities contained in said erase gate and said control gate are approximately equal to a solution limit, and the impurity density of the impurity contained in said floating gate is less than said solution limit.
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JPS60250676A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-02-25 | 1994-08-27 | 1995-02-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-02-25 | 1998-08-27 | 1999-02-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-02-25 | 2002-08-27 | 2003-02-26 | $7700.00 | Window Closed / Lapsed |