EP0144900A2
Expired / Lapsed
EP
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An electrically programmable memory device and a method for making the same
Assignee: Rohm Corp
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Filing: 1984-11-27
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Granted: —
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Expires: 2004-11-27
Abstract
Abstract In the present invention, asperity in the floating gate of an EPROM or EEPROM device is reduced. An improved process for fabricating ultrahigh coupling interpoly isolation dielectrics comprising a structure of oxide-nitride-oxide is disclosed. The first oxide is grown on undoped LPCVD polycrystalline silicon (polysilicon) to reduce the grain boundary-oxidation enhancement effect at the interface of floating gate polysilicon and interpoly oxide. This results in much higher breakdown capability of interpoly dielectrics. As a consequence, the shrinkage of the interpoly electrical thickness to an extent far beyond current limitation becomes possible. Implanted dopants through interpoly oxide into the floating gate polysilicon also eliminate the oxidation enhanced diffusion from conventional POCI 3 doped polysilicon into tunnel oxide. The phosphorus induced trap in the tunnel oxide region are reduced. The EEPROM threshold window can remain open beyond 10 6 cycles.
Inventors
- 👤 Thomas T. L. Chang
- 👤 Chun Ho
- 👤 Arun Kumar Malhotra
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 18:02
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/69; H10D30/68; H10D30/681; H10D30/683; H10D64/00; H10D64/01; H10D64/031; H10D64/035
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
132 words
A method of making an electrically programmable memory device of the type having a plurality of electrical connections and a floating gate for storing charges therein, said method comprising the steps of fabricating a body of single crystalline semiconductive material having at least one said connections; thermally growing a first layer of insulating material on said body of semiconductive material; depositing a first layer of semiconductive material on said first layer of insulating material; thermally growing a second layer of insulating material on said first layer of semiconductive material; implanting a doping material through said second layer of insulating material into said first layer of semiconductive material to form said floating gate; and depositing a second layer of semiconductive material over said second layer of insulating material and forming an electrical connection.
Claim 2
Independent Claim
132 words
A method of making an electrically programmable memory device of the type having a plurality of electrical connections and a floating gate for storing charges therein, said method comprising the steps of fabricating a body of single crystalline semiconductive material having at least one said connections; thermally growing a first layer of insulating material on said body of semiconductive material; depositing a first layer of semiconductive material on said first layer of insulating material; thermally growing a second layer of insulating material on said first layer of semiconductive material; implanting a doping material through said second layer of insulating material into said first layer of semiconductive material to form said floating gate; and depositing a second layer of semiconductive material over said second layer of insulating material and forming an electrical connection.
Claim 3
Dependent Claim
25 words
The method of Claim 1, wherein said body of single crystalline semiconductive material and said first and second layers of semiconductive material are of silicon.
Claim 4
Dependent Claim
16 words
The method of Claim 2, wherein said first and second layers of silicon are polycrystalline silicon.
Claim 5
Dependent Claim
19 words
The method of Claim 2, wherein said first and second layers of insulating material are of silicon dioxide (Si02).
Claim 6
Dependent Claim
19 words
The method of Claim 3, wherein said first layer of polycrystalline silicon is deposited by low pressure chemical-vapor deposition.
Claim 7
Dependent Claim
13 words
The method of Claim 1, wherein said implanting step is by ion implantation.
Claim 8
Dependent Claim
11 words
The method of Claim 5, wherein said doping material is phosphorus.
Claim 9
Dependent Claim
55 words
the method of Claim 1 after said implanting step further comprising the steps of removing a portion of said second layer of insulating material; and depositing a third layer of insulating material on said second layer of insulating material; wherein said second layer of conductive material being deposited on said third layer of insulting material.
Claim 10
Dependent Claim
25 words
The method of Claim 8, wherein said body of single crystalline semiconductive material and said first and second layers of semiconductive material are of silicon.
Claim 11
Dependent Claim
16 words
The method of Claim 9, wherein said first and second layers of silicon are polycrystalline silicon.
Claim 12
Dependent Claim
21 words
The method of Claim 9, wherein said first and second layers of insulating material are of silicon dioxide (SiO 2 ).
Claim 13
Dependent Claim
18 words
The method of Claim 11, wherein said third layer of insulating material is Si 3 N 4 .
Claim 14
Dependent Claim
20 words
The method of Claim 11, wherein said first layer of polycrystalline silicon is deposited by low pressure chemical vapor deposition.
Claim 15
Dependent Claim
13 words
The method of Claim 8, wherein said implanting step is by ion implantation.
Claim 16
Dependent Claim
11 words
The method of Claim 13, wherein said doping material is phosphorus.
Claim 17
Dependent Claim
21 words
The method of Claim 15, wherein said removing step comprises exposing said second layer of SiO 2 to dilute HF acid.
Claim 18
Dependent Claim
36 words
The method of Claim 16 further comprising the step of exposing said third layer of insulating material to pyrogenic (H 2/ 0 2 ) oxidation, forming a fourth layer of insulating material of Si0 2 .
Claim 19
Dependent Claim
69 words
The method of Claim 17, wherein said depositing step for the first layer of polycrystalline silicon forms approximately 3000-4000 angstroms; said depositing step for the second layer of SiO 2 forms substantially 250 angstroms; said removing step removes substantially 20 angstroms of Si0 2 ; said depositing step for the third layer of Si 3 N 4 forms substantially 250 angstroms; and said fourth layer is substantially 30-50 angstroms.
Claim 20
Independent Claim
82 words
A method of reducing asperity in the floating gate of an electrically programmable memory device, said floating gate positioned between a first layer of insulating material and a second layer of insulating material and being of a semiconductive material, doped with a dopant, where said improvement comprising depositing said semiconductive material on said first layer; thermally growing said second layer on said 10 semiconductive material; and ion implanting said dopant through said second layer into said semiconductive material forming said floating gate.
Claim 21
Independent Claim
82 words
A method of reducing asperity in the floating gate of an electrically programmable memory device, said floating gate positioned between a first layer of insulating material and a second layer of insulating material and being of a semiconductive material, doped with a dopant, where said improvement comprising depositing said semiconductive material on said first layer; thermally growing said second layer on said 10 semiconductive material; and ion implanting said dopant through said second layer into said semiconductive material forming said floating gate.
Claim 22
Dependent Claim
27 words
The method of Claim 19, wherein said first and second layers are of SiO 2 ; said semiconductive material is polycrystalline silicon; and said dopant is phosphorus.
Claim 23
Dependent Claim
107 words
21 . An electrically programmable memory device comprising a body of single crystalline semiconductive material having a source and a drain; a first layer of insulating material on said body; a floating gate on said first layer; a second layer of insulating material on said floating gate; said floating gate formed by depositing a layer of semiconductive material on said first layer of insulating material; thermally growing said second layer of insulating material on said layer of semiconductive material; and ion implanting a dopant through said second layer of insulating material into said layer of semiconductive material; and a gate over said second layer of insulating material.
Claim 24
Dependent Claim
107 words
21 . An electrically programmable memory device comprising a body of single crystalline semiconductive material having a source and a drain; a first layer of insulating material on said body; a floating gate on said first layer; a second layer of insulating material on said floating gate; said floating gate formed by depositing a layer of semiconductive material on said first layer of insulating material; thermally growing said second layer of insulating material on said layer of semiconductive material; and ion implanting a dopant through said second layer of insulating material into said layer of semiconductive material; and a gate over said second layer of insulating material.
Claim 25
Dependent Claim
26 words
The device of Claim 21 further comprising a third layer of insulating material on said second layer of insulating material; said gate on said third layer.
Claim 26
Dependent Claim
15 words
The device of Claim 21, wherein said body and said floating gate is of silicon.
Claim 27
Dependent Claim
12 words
The device of Claim 23, wherein said floating gate is of polycrystalline.
Claim 28
Dependent Claim
28 words
25 . The device of Claim 24, wherein each of said first and second layers of insulating material is of Si0 2 , and said dopant is phosphorus.
Claim 29
Dependent Claim
15 words
The device of Claim 22, wherein said body and said floating gate is of silicon.
Claim 30
Dependent Claim
12 words
The device of Claim 26, wherein said floating gate is of polycrystalline.
Claim 31
Dependent Claim
26 words
The device of Claim 27, wherein each of said first and second layers of insulating material is of SiO 2 , and said dopant is phosphorus.
Claim 32
Dependent Claim
16 words
The device of Claim 28, wherein said third layer is of Si 3 N 4 .
Claim 33
Dependent Claim
59 words
The device of Claim 29, wherein said first layer of Si0 2 is approximately 750 angstroms over the thick gate area and approximately 100 angstroms over the thin gate area; said floating gate is substantially 3000-4500 angstroms; said second layer of SiO 2 is substantially 230 angstroms; and said layer of Si 3 N 4 is substantially 250 angstroms.
References Cited (Backward Citations)
No citation records indexed.
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