US4437174A
Expired / Lapsed
US
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Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1981-11-13
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Granted: 1984-03-13
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Expires: 2001-11-13
Abstract
Abstract A semiconductor memory device consisting of memory cells each of which has an erase gate for erasing data from the floating gate thereof. The semiconductor memory device has a circuit for applying an erase voltage of high level to the erase gate to erase data from the floating gate. The semiconductor memory device further includes a circuit for applying a predetermined potential difference between the drain and the source of a selected memory cell so as to detect a current flowing through the selected memory cell, thereby detecting the data erasure condition from the floating gate of the selected memory cell. A circuit is also included for inhibiting the application of the erase voltage upon detection of the current flowing through the memory cell.
Inventors
- 👤 Fujio Masuoka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 02:33
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3436; G11C16/3468; G11C16/3477; G11C16/10; G11C16/14; H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
342 words
A semiconductor memory device comprising: a memory matrix having a plurality of memory cells arranged in a matrix form, each of said plurality of memory cells including a semiconductor region of first conductivity type, a source region and a drain region of second conductivity type, an erase gate formed on said semiconductor region with a first insulating film interposed between said erase gate and said semiconductor region, a floating gate which is formed on said semiconductor region with a second insulating film being interposed between said floating gate and said semiconductor region, said floating gate being capable of storing data and overlapping said erase gate, and with a third insulating film being interposed between said floating gate and said erase gate, and a control gate which is formed on said floating gate with a fourth insulating film being interposed between said control gate and said floating gate and said control gate being insulated from said erase gate and said floating gate; a row line commonly connected to said control gates of said memory cells of each row of said memory matrix; a column line commonly connected to said sources or drains of said memory cells of each column of said memory matrix; an erase line commonly connected to said erase gates of said memory cells of each column of said memory matrix; first applying means for applying an erase voltage having a high level to said erase gate of said memory cell to erase data from said floating gate thereof, said memory cell being connected to said row line, said column line and said erase line which are selected; second applying means for applying a voltage of a predetermined level to said selected column line to detect a data erasure condition of said memory cells which is selected; means for inhibiting supply of said erase voltage when a current flowing through said column line is detected; and third applying means for applying a voltage of low level to said selected row line when data is erased and when data erasure is detected.
Claim 2
Dependent Claim
342 words
A semiconductor memory device comprising: a memory matrix having a plurality of memory cells arranged in a matrix form, each of said plurality of memory cells including a semiconductor region of first conductivity type, a source region and a drain region of second conductivity type, an erase gate formed on said semiconductor region with a first insulating film interposed between said erase gate and said semiconductor region, a floating gate which is formed on said semiconductor region with a second insulating film being interposed between said floating gate and said semiconductor region, said floating gate being capable of storing data and overlapping said erase gate, and with a third insulating film being interposed between said floating gate and said erase gate, and a control gate which is formed on said floating gate with a fourth insulating film being interposed between said control gate and said floating gate and said control gate being insulated from said erase gate and said floating gate; a row line commonly connected to said control gates of said memory cells of each row of said memory matrix; a column line commonly connected to said sources or drains of said memory cells of each column of said memory matrix; an erase line commonly connected to said erase gates of said memory cells of each column of said memory matrix; first applying means for applying an erase voltage having a high level to said erase gate of said memory cell to erase data from said floating gate thereof, said memory cell being connected to said row line, said column line and said erase line which are selected; second applying means for applying a voltage of a predetermined level to said selected column line to detect a data erasure condition of said memory cells which is selected; means for inhibiting supply of said erase voltage when a current flowing through said column line is detected; and third applying means for applying a voltage of low level to said selected row line when data is erased and when data erasure is detected.
Claim 3
Dependent Claim
19 words
A semiconductor memory device according to claim 1, wherein data erasure and detection of data erasure are performed simultaneously.
Claim 4
Dependent Claim
19 words
A semiconductor memory device according to claim 1, wherein data erasure and detection of data erasure are alternately performed.
Claim 5
Dependent Claim
76 words
A semiconductor memory device according to claim 1, wherein said inhibiting means comprises: a plurality of sense amplifiers one end each of which is connected to said column line and the other end each of which is connected to each output end of a column decoder; a gate transistor arranged for each of said erase lines; and a booster connected to a gate of said gate transistor and to the output end of said column decoder.
Claim 6
Dependent Claim
167 words
A semiconductor memory device according to claim 4, wherein each of said sense amplifiers comprises: a first inverter circuit an input end of which is connected to the output end of said column decoder and an output end of which is connected to said column line, said first inverter circuit consisting of a series connection of an even number of inverters; a MOS transistor interposed between the output end of said column decoder and a point of ground potential; a second inverter circuit an input end of which is connected to said column line and which consists of a series connection of an odd number of inverters; and a latch circuit to which is input an output from said second inverter circuit and an output end of which is connected to a gate of said MOS transistor, a reset signal being input to said latch circuit in order to set the output end of said latch circuit at low level before initiating detection of data erase condition.
Claim 7
Dependent Claim
147 words
A semiconductor memory device according to claim 1, wherein said inhibiting means comprises: a sense amplifier having an input end which is connected to an input end of said column decoder and which is constituted by an odd number of inverters connected in series; a latch circuit having an input connected to an output from said sense amplifier, a reset signal being supplied to said latch circuit in order to set an output end of said latch circuit at a low level before initiating detection of data erasure condition; a first MOS transistor a gate of which is connected to the output end of said latch circuit and one end of which first MOS transistor is grounded; and a second MOS transistor which is arranged for each of said column lines and a gate of which is connected to the other end of said first MOS transistor.
References Cited (Backward Citations)
US4203158A
Cited
US4203158B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-03-13 | 1987-09-12 | 1988-03-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-03-13 | 1991-09-12 | 1992-03-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-03-13 | 1995-09-12 | 1996-03-13 | $7700.00 | Window Closed / Lapsed |