Trench resistor structures for compact semiconductor memory and logic devices

Claim 2

A trench interconnection structure comprising: a layer of semiconductor material having a top surface, said layer formed of semiconductor material of first conductivity type; a buried region spaced apart from said top surface of said layer of semiconductor material; a trench having an aperture at said top surface of said layer of semiconductor material and also having essentially vertical sidewalls extending into said layer of semiconductor material and into said buried region; and interconnect material of a second conductivity type opposite said first conductivity type located within said trench and in contact with said layer of semiconductor material along at least a portion of said vertical sidewalls, and having a top surface near said top surface of said layer of semiconductor material, said interconnect material forming a vertical trench electrical interconnection between said top surface of said interconnect material and said buried region.

Claim 3

A trench interconnection structure comprising: a layer of semiconductor material having a top surface, said layer formed of semiconductor material of first conductivity type; a buried region spaced apart from said top surface of said layer of semiconductor material; a trench having an aperture at said top surface of said layer of semiconductor material and also having essentially vertical sidewalls extending into said layer of semiconductor material and into said buried region; interconnect material located within said trench and in contact with said layer of semiconductor material along at least a portion of said vertical sidewalls, and having a top surface near said top surface of said layer of semiconductor material, said interconnect material forming a vertical trench electrical interconnection between said top surface of said interconnect material and said buried region; and a layer of insulating material covering said vertical sidewalls of said trench, wherein said insulating material does not cover said buried region and said top surface at said aperture.

Claim 4

A trench interconnection structure comprising: a layer of semiconductor material having a top surface, said layer formed of semiconductor material of first conductivity type; a buried region spaced apart from said top surface of said layer of semiconductor material; a trench having an aperture at said top surface of said layer of semiconductor material and also having essentially vertical sidewalls extending into said layer of semiconductor material and into said buried region; interconnect material located within said trench and in contact with said layer of semiconductor material along at least a portion of said vertical sidewalls, and having a top surface near said top surface of said layer of semiconductor material, said interconnect material forming a vertical trench electrical interconnection between said top surface of said interconnect material and said buried region; and a layer of insulating material covering said vertical sidewalls of said trench, wherein said insulating material does not cover said buried region and said top surface at said aperture.

Claim 5

A trench interconnection structure as in claim 1 wherein said aperture of said trench is less than 2 microns across at its widest point and the depth of said trench is between 1 and 10 microns.

Claim 6

A trench interconnection structure as in claim 1 wherein said layer of semiconductor material comprises silicon.

Claim 7

A trench interconnection structure as in claim 1 which further comprises a semiconductor substrate, and said buried region is formed within said semiconductor substrate and more heavily doped than said semiconductor substrate, and wherein said layer of semiconductor material comprises an epitaxial layer formed on said semiconductor substrate.

Claim 8

A trench interconnection structure as in claim 5 wherein said epitaxial layer is formed on said semiconductor substrate after the formation of said buried region.

Claim 9

A trench interconnection structure as in claim 1 which further comprises a semiconductor substrate, at least a portion of which serves as said buried region, and wherein said layer of semiconductor material comprises an epitaxial layer formed on said semiconductor substrate.

Claim 10

A trench interconnection structure as in claims 1 or 2 wherein said interconnect material comprises polycrystalline silicon.

Claim 11

A trench interconnection structure as in claim 8 wherein said polycrystalline silicon is undoped or lightly doped, thereby having a high resistivity.

Claim 12

A trench interconnection structure as in claim 9 wherein said polycrystalline silicon serves as a resistor.

Claim 13

A trench interconnection structure as in claim 1 wherein said interconnect material is formed in a layer covering said sidewalls of said trench, further comprising a filler material within the portion of said trench not covered by said interconnect material.

Claim 14

A trench interconnection structure as in claim 11 wherein said filler material has a higher resistivity than said interconnect material.

Claim 15

A trench interconnection structure as in claim 12 wherein said interconnect material comprises undoped polycrystalline silicon, doped polycrystalline silicon, or polycrystalline silicide, and said filler material comprises doped polycrystalline silicon, undoped polycrystalline silicon, silicon dioxide, or silicon nitride. pg,44

Claim 16

A very high resistivity trench resistor structure as in claim 8 wherein the electrical resistance between said top surface of said interconnect material and said buried region is between approximately 1×10 6 and 1×10 12 ohms.

Claim 17

A very high resistivity trench resistor structure as in claim 11 wherein the electrical resistance between said top surface of said interconnect material and said buried region is between approximately 1×10 6 and 1×10 12 ohms.

Claim 18

A medium resistivity trench resistor structure as in claim 8 wherein said interconnect material is more heavily doped so as to reduce the electrical resistance between said top surface of said interconnect material and said buried region to between approximately 50 and 10 4 ohms.

Claim 19

A medium resistivity trench resistor structure as in claim 11 wherein said interconnect material is heavily doped so as to reduce the electrical resistance between said top surface of said interconnect material and said buried region to between approximately 50 and 10 4 ohms.

Claim 20

A very low resistivity trench connector structure as in claims 1 or 2 wherein said interconnect material comprises a low resistivity material.

Claim 21

A very low resistivity trench connector structure as in claim 11 wherein said interconnect material comprises a low resistivity material.

Claim 22

A very low resistivity trench connector structure as in claim 11 wherein said interconnect material comprises tungsten silicide or tungsten formed by low pressure chemical vapor deposition of sufficient thickness to fill the cavity of said trench but deposited under selective deposition conditions favoring the deposition on the exposed surface of said trench but not on any other surface protected with a dielectric film.

Claim 23

A trench interconnection structure as in claim 12 which further comprises a semiconductor substrate, and wherein said buried regions are formed within said semiconductor substrate and are more heavily doped than said semiconductor substrate, and wherein said layer of semiconductor material comprises an epitaxial layer formed on said semiconductor substrate.

Claim 24

The structure of claim 21 wherein a supply voltage is applied to said substrate and said supply voltage is delivered to selected ones of said top surfaces of said regions of interconnect material.

Claim 25

The structure of claim 7 wherein a supply voltage is applied to said substrate and said supply voltage is delivered to said top surface of said region of interconnect material through said trench interconnect structure.

Claim 26

The structure of claims 1 or 2 which further comprises a doped region located near said top surface of said layer of semiconductor material, said doped region making direct electrical contact to said interconnect material at said aperture.

Claim 27

The structure of claim 24 wherein said buried region and said doped region located near said top surface are of a second conductivity type opposite said first conductivity type.

Claim 28

The structure of claims 1 or 2 which further comprises a gate electrode formed on a gate oxide on said top surface of said layer of semiconductor material, said gate electrode making electrical contact to said interconnect material through a buried contact opening in said gate oxide at said aperture.

Claim 29

An MOS logic inverter comprising: an input terminal; an output terminal; a resistive load formed of a trench resistor comprising: a layer of semiconductor material having a top surface, said layer formed of semiconductor material of first conductivity type; buried region spaced apart from said top surface of said layer of semiconductor material; a trench having an aperture at said top surface of said layer of semiconductor material and also having essentially vertical sidewalls extending into said layer of semiconductor material and into said buried region; a layer of insulating material covering those portions of said vertical sidewalls of said trench which are above said buried region and below said top surface of said semiconductor material; and interconnect material located within said trench and having a top surface near said top surface of said layer of semiconductor material and a bottom surface in contact with said buried region, said interconnect material forming a vertical trench electrical interconnection between said top surface of said interconnect material and said buried region; and a switching transistor having: a source diffusion connected to one supply voltage; a drain diffusion connected to said output terminal as well as to said top surface of said trench resistor through said aperture; and a gate connected to said output terminal, wherein the second supply voltage is applied to the buried end of said trench resistor through said bottom surface of said trench resistor to said buried region.

Claim 30

An MOS logic inverter comprising: an input terminal; an output terminal; a resistive load formed of a trench resistor comprising: a layer of semiconductor material having a top surface, said layer formed of semiconductor material of first conductivity type; buried region spaced apart from said top surface of said layer of semiconductor material; a trench having an aperture at said top surface of said layer of semiconductor material and also having essentially vertical sidewalls extending into said layer of semiconductor material and into said buried region; a layer of insulating material covering those portions of said vertical sidewalls of said trench which are above said buried region and below said top surface of said semiconductor material; and interconnect material located within said trench and having a top surface near said top surface of said layer of semiconductor material and a bottom surface in contact with said buried region, said interconnect material forming a vertical trench electrical interconnection between said top surface of said interconnect material and said buried region; and a switching transistor having: a source diffusion connected to one supply voltage; a drain diffusion connected to said output terminal as well as to said top surface of said trench resistor through said aperture; and a gate connected to said output terminal, wherein the second supply voltage is applied to the buried end of said trench resistor through said bottom surface of said trench resistor to said buried region.

Claim 31

A structure as in claim 27 wherein said electrical interconnection has a resistance within the range of approximately 1×10 6 to 1×10 12 ohms.

Claim 32

A structure as in claim 27 wherein said electrical interconnection has a resistance within the range of approximately 50 to 1×10 4 ohms.

Claim 33

An MOS bistable static storage element comprising two cross-coupled inverters wherein each of said cross-coupled inverters comprises: an input terminal; an output terminal connected to the input terminal of the other inverter; a resistive load of a trench resistor comprising: a layer of semiconductor material having a top surface, said layer formed of semiconductor material of first conductivity type; a buried region spaced apart from said top surface of said layer of semiconductor material; a trench having an aperture at said top surface of said layer of semiconductor material and also having essentially vertical sidewalls extending into said layer of semiconductor material and into said buried region; a layer of insulating material covering those portions of said vertical sidewalls of said trench which are above said buried region and below said top surface of said semiconductor material; and interconnect material located within said trench and having a top surface near said top surface of said layer of semiconductor material and a bottom surface in contact with said buried region, said interconnect material forming a vertical trench electrical interconnection between said top surface of said interconnect material and said buried region; and a switching transistor having: a source diffusion connected to one supply voltage; a drain diffusion connected to said output terminal as well as to said top surface of said trench resistor through said top electrical contact means; and a gate connected to said input terminal, wherein the second supply voltage is applied to the buried end of said trench resistor through said bottom surface of said trench resistor to said buried region.

Claim 34

An MOS bistable static storage element comprising two cross-coupled inverters wherein each of said cross-coupled inverters comprises: an input terminal; an output terminal connected to the input terminal of the other inverter; a resistive load of a trench resistor comprising: a layer of semiconductor material having a top surface, said layer formed of semiconductor material of first conductivity type; a buried region spaced apart from said top surface of said layer of semiconductor material; a trench having an aperture at said top surface of said layer of semiconductor material and also having essentially vertical sidewalls extending into said layer of semiconductor material and into said buried region; a layer of insulating material covering those portions of said vertical sidewalls of said trench which are above said buried region and below said top surface of said semiconductor material; and interconnect material located within said trench and having a top surface near said top surface of said layer of semiconductor material and a bottom surface in contact with said buried region, said interconnect material forming a vertical trench electrical interconnection between said top surface of said interconnect material and said buried region; and a switching transistor having: a source diffusion connected to one supply voltage; a drain diffusion connected to said output terminal as well as to said top surface of said trench resistor through said top electrical contact means; and a gate connected to said input terminal, wherein the second supply voltage is applied to the buried end of said trench resistor through said bottom surface of said trench resistor to said buried region.

Claim 35

A structure as in claim 30 wherein said vertical trench resistor has a resistance within the range of approximately 1×10 6 to 1×10 12 ohms.

Claim 36

An array of MOS static random access memory cells wherein the bistable storage element of each cell comprises two cross-coupled inverters, wherein each of said cross-coupled inverters comprise: an input terminal; an output terminal connected to the terminal of the other inverter; a resistor load formed of a high resistivity trench resistor comprising: a layer of semiconductor material having a top surface, said layer formed of semiconductor material of first conductivity type; a buried region spaced apart from said top surface of said layer of semiconductor material; a trench having an aperture at said top surface of said layer of semiconductor material and also having essentially vertical sidewalls extended into said layer of semiconductor material and into said buried region and below said top surface of said semiconductor material; a layer of insulating material covering those portions of said vertical sidewalls of said trench which are above said buried region and below said top surface of said semiconductor material; and interconnect material located within said trench and having a top surface near said top surface of said layer of semiconductor material and a bottom surface in contact with said buried region, said interconnect material forming a vertical trench electrical interconnection between said top surface of said interconnect material and said buried region; and a switching transistor having: a source diffusion connected to one supply voltage; a drain diffusion connected to said output terminal as well as to said top surface of said trench resistor; and a gate connected to said input terminal, wherein the second supply voltage is applied to the buried end of said trench resistor through said bottom surface of said trench resistor to said buried region.

Claim 37

An array of MOS static random access memory cells wherein the bistable storage element of each cell comprises two cross-coupled inverters, wherein each of said cross-coupled inverters comprise: an input terminal; an output terminal connected to the terminal of the other inverter; a resistor load formed of a high resistivity trench resistor comprising: a layer of semiconductor material having a top surface, said layer formed of semiconductor material of first conductivity type; a buried region spaced apart from said top surface of said layer of semiconductor material; a trench having an aperture at said top surface of said layer of semiconductor material and also having essentially vertical sidewalls extended into said layer of semiconductor material and into said buried region and below said top surface of said semiconductor material; a layer of insulating material covering those portions of said vertical sidewalls of said trench which are above said buried region and below said top surface of said semiconductor material; and interconnect material located within said trench and having a top surface near said top surface of said layer of semiconductor material and a bottom surface in contact with said buried region, said interconnect material forming a vertical trench electrical interconnection between said top surface of said interconnect material and said buried region; and a switching transistor having: a source diffusion connected to one supply voltage; a drain diffusion connected to said output terminal as well as to said top surface of said trench resistor; and a gate connected to said input terminal, wherein the second supply voltage is applied to the buried end of said trench resistor through said bottom surface of said trench resistor to said buried region.

Claim 38

The array of MOS static random access memory cells of claim 32 wherein a plurality of adjacent cells share a common one of said buried regions.

Claim 39

A bipolar logic inverter comprising: an input terminal; an output terminal; a resistive load formed of a trench resistor comprising: a layer of semiconductor materail having a top surface, said layer formed of semiconductor material of first conductivity type; a first buried region spaced apart from said top surface of said layer of semiconductor material; a trench having an aperture at said top surface of said layer of semiconductor material and also having essentially vertical sidewalls extending into said layer of semiconductor material and into said first buried region; a layer of insulating material covering at least those portions of said vertical sidewalls of said trench which are above said buried region; and interconnect material located within said trench and having a top surface near said top surface of said layer of semiconductor material and a bottom surface in contact with said first buried region, said interconnect material forming a vertical trench resistor between said top surface of said interconnect material and said first buried region; and a switching transistor comprising: an emitter connected to a first supply voltage; a collector connected to said output terminal of said inverter and to a first end of said trench resistor; and a base connected to said input lead of said inverter; and means for connecting a second supply voltage to the second end of said trench resistor.

Claim 40

A bipolar logic inverter comprising: an input terminal; an output terminal; a resistive load formed of a trench resistor comprising: a layer of semiconductor materail having a top surface, said layer formed of semiconductor material of first conductivity type; a first buried region spaced apart from said top surface of said layer of semiconductor material; a trench having an aperture at said top surface of said layer of semiconductor material and also having essentially vertical sidewalls extending into said layer of semiconductor material and into said first buried region; a layer of insulating material covering at least those portions of said vertical sidewalls of said trench which are above said buried region; and interconnect material located within said trench and having a top surface near said top surface of said layer of semiconductor material and a bottom surface in contact with said first buried region, said interconnect material forming a vertical trench resistor between said top surface of said interconnect material and said first buried region; and a switching transistor comprising: an emitter connected to a first supply voltage; a collector connected to said output terminal of said inverter and to a first end of said trench resistor; and a base connected to said input lead of said inverter; and means for connecting a second supply voltage to the second end of said trench resistor.

Claim 41

The bipolar logic inverter of claim 34 wherein said first end of said trench resistor comprises said top surface of said interconnect material, and said second end of said trench resistor comprises said bottom surface of said interconnect material.

Claim 42

The bipolar logic inverter of claim 35 further comprising: a second buried region serving as said collector of said transistor; and a first trench interconnection structure for providing low resistance electrical connection of said second supply voltage to said first buried region, and a second trench interconnection structure for providing low resistance electrical connection of said second buried region to said output terminal, each of said first and second trench interconnection structures comprising: a trench having an aperture at said top surface of said layer of semiconductor material and also having essentially vertical sidewalls extending into said layer of semiconductor material and into its associated one of said buried region; a layer of insulating material covering at least those portions of said vertical sidewalls of said trench which are above said buried region; and interconnect material located within said trench and having a top surface near said top surface of said layer of semiconductor material and a bottom surface in contact with said buried region, said interconnect material forming a low resistivity vertical trench electrical interconnection between said top surface of said interconnect material and said buried region.

Claim 43

The inverter of claim 34 wherein said collector is connected to said output terminal of said inverter and through said first buried region to said bottom surface of said trench resistor and said second supply voltage is connected to said top surface of said interconnect material.

Claim 44

The inverter of claim 37 wherein said collector is merged with said first buried region and said first buried region is connected to said output terminal through a trench interconnection structure comprising: a trench having an aperture at said top surface of said layer of semiconductor material and also having essentially vertical sidewalls extending into said layer of semiconductor material and into its associated one of said buried regions; a layer of insulating material covering at least those portions of said vertical sidewalls of said trench which are above said buried region; and interconnect material located within said trench and having a top surface near said top surface of said layer of semiconductor material and a bottom surface in contact with said buried region, said interconnect material forming a low resistivity vertical trench electrical interconnection between said top surface of said interconnect material and said buried region.

Claim 45

A bipolar bistable static storage element comprising two cross-coupled bipolar logic inverters wherein each of said cross-coupled inverters comprises: an input terminal; an output terminal connected to the input terminal of the other inverter; a resistive load formed of a trench resistor comprising: a layer of semiconductor material having a top surface, said layer formed of semiconductor material of first conductivity type; a first buried region spaced apart from said top surface of said layer of semiconductor material; a trench having an aperture at said top surface of said layer of semiconductor material and also having essentially vertical side-walls extended into said layer of semiconductor material and into said first buried region; a layer of insulating material covering at least those portions of said vertical sidewalls of said trench which are above said buried region; and interconnect material located within said trench and having a top surface near said top surface of said layer of semiconductor material and a bottom surface in contact with said buried region, said interconnect material forming a vertical trench electrical resistor between said top surface of said interconnect material and said buried region; and a switching transistor comprising: an emitter connected to a first supply voltage; a collector connected to said output terminal of said inverter and to a first end of said trench resistor; and a base connected to said input lead of said inverter; and means for connecting a second supply voltage to the second end of said trench resistor.

Claim 46

A bipolar bistable static storage element comprising two cross-coupled bipolar logic inverters wherein each of said cross-coupled inverters comprises: an input terminal; an output terminal connected to the input terminal of the other inverter; a resistive load formed of a trench resistor comprising: a layer of semiconductor material having a top surface, said layer formed of semiconductor material of first conductivity type; a first buried region spaced apart from said top surface of said layer of semiconductor material; a trench having an aperture at said top surface of said layer of semiconductor material and also having essentially vertical side-walls extended into said layer of semiconductor material and into said first buried region; a layer of insulating material covering at least those portions of said vertical sidewalls of said trench which are above said buried region; and interconnect material located within said trench and having a top surface near said top surface of said layer of semiconductor material and a bottom surface in contact with said buried region, said interconnect material forming a vertical trench electrical resistor between said top surface of said interconnect material and said buried region; and a switching transistor comprising: an emitter connected to a first supply voltage; a collector connected to said output terminal of said inverter and to a first end of said trench resistor; and a base connected to said input lead of said inverter; and means for connecting a second supply voltage to the second end of said trench resistor.

Claim 47

The bipolar logic inverter of claim 39 wherein, for each of said inverters, said first end of said trench resistor comprises said top surface of said interconnect material, and said second end of said trench resistor comprises said bottom surface of said interconnect material which is in contact with said first buried region.

Claim 48

The bipolar logic inverter of claim 40 further comprising: a second buried region serving as said collector of said transistor; and a first trench interconnection structure for providing low resistance electrical connection of said second supply voltage to said first buried region, and a second trench interconnection structure for providing low resistance electrical connection of said second buried region to said output terminal, each of said first and second trench interconnection structures comprising: a trench having an aperture at said top surface of said layer of semiconductor material and also having essentially vertical sidewalls extending into said layer of semiconductor material and into its associated one of said buried regions; a layer of insulating material covering at least those portions of said vertical sidewalls of said trench which are above said buried region; and low resistivity interconnect material located within said trench and having a top surface near said top surface of said layer of semiconductor material, said interconnect material forming a vertical trench electrical interconnection between said top surface of said interconnect material and said buried region.

Claim 49

The bipolar bistable static storage element of claim 39 wherein, for each of said inverters, said collector is connected to said output terminal of said inverter and through said first buried region to said bottom surface of said trench resistor and said second supply voltage is connected to said top surface of said interconnect material.

Claim 50

The bipolar bistable static storage element of claim 42 wherein for each of said inverters, said collector is merged with said first buried region and said buried region is connected to said output terminal through a trench interconnection structure comprising: a trench having an aperture at said top surface of said layer of semiconductor material and also having essentially vertical sidewalls extending into said layer of semiconductor material and into its associated one of said buried regions; a layer of insulating material covering at least those portions of said vertical sidewalls of said trench which are above said buried region; and interconnect material located within said trench and having a top surface near said top surface of said layer of semiconductor material and a bottom surface in contact with said buried region, said interconnect material forming a low resistivity vertical trench electrical interconnection between said top surface of said interconnect material and said buried region.

Claim 51

A BICMOS structure formed in a layer of semiconductor material having a top surface comprising NMOS transistors, PMOS transistors, vertical NPN transistors, and a plurality of doped buried regions wherein any one of said doped buried regions are electrically contacted from the top surface with a low resistivity trench connector structure comprising: a trench having an aperture at said top surface of said layer of semiconductor material and also having essentially vertical sidewalls extending into said layer of semiconductor material and into said buried region; and interconnect material located within said trench and in contact with said layer of semiconductor material along at least a portion of said vertical sidewalls and having a top surface near said top surface of said layer of semiconductor material, said interconnect material forming a vertical trench electrical interconnection between said top surface of said interconnect material and said buried region.

Claim 52

A BICMOS structure formed in a layer of semiconductor material having a top surface comprising NMOS transistors, PMOS transistors, vertical NPN transistors, and a plurality of doped buried regions wherein any one of said doped buried regions are electrically contacted from the top surface with a low resistivity trench connector structure comprising: a trench having an aperture at said top surface of said layer of semiconductor material and also having essentially vertical sidewalls extending into said layer of semiconductor material and into said buried region; and interconnect material located within said trench and in contact with said layer of semiconductor material along at least a portion of said vertical sidewalls and having a top surface near said top surface of said layer of semiconductor material, said interconnect material forming a vertical trench electrical interconnection between said top surface of said interconnect material and said buried region.

Claim 53

A trench interconnection structure as in claim 44 wherein said vertical sidewalls of said trench are covered with a layer of insulating material wherein said insulating material does not cover said buried region and said top surface at said aperture.

Claim 54

A very low resistivity trench connector structure as in claims 44 or 45 wherein said interconnect material comprises a low resistivity material such as policides, silicides, or refractory metals, thereby providing an electrical resistance between said top surface of said interconnect material and said buried region of less than approximately 10 ohms.

Claim 55

An integrated circuit wherein selected portions are electrically segregated from one another by surrounding each of said selected portions with very low resistivity trench connectors formed in long, narrow and deep trench segregation walls surrounding partially or completely said selected portions, wherein said low resistivity trench connectors comprise: a trench having a long and narrow aperture at the top surface of a layer of semiconductor material and also having essentially vertical sidewalls extending deep into said layer of semiconductor material; and interconnect material located within said trench and in contact with said layer of semiconductor material along at least a portion of said vertical sidewalls, and having a top surface near said top surface of said layer of semiconductor material, said interconnect material forming a vertical trench electrical segregation wall between adjacent ones of said portions.

Claim 56

An integrated circuit wherein selected portions are electrically segregated from one another by surrounding each of said selected portions with very low resistivity trench connectors formed in long, narrow and deep trench segregation walls surrounding partially or completely said selected portions, wherein said low resistivity trench connectors comprise: a trench having a long and narrow aperture at the top surface of a layer of semiconductor material and also having essentially vertical sidewalls extending deep into said layer of semiconductor material; and interconnect material located within said trench and in contact with said layer of semiconductor material along at least a portion of said vertical sidewalls, and having a top surface near said top surface of said layer of semiconductor material, said interconnect material forming a vertical trench electrical segregation wall between adjacent ones of said portions.

Claim 57

A very low resistivity trench connector structure as in claim 47 wherein said interconnect material comprises a low resistivity material.

Claim 58

A very low resistivity trench connector structure as in claim 47 wherein said interconnect material comprises tungsten silicide to tungsten formed by low pressure chemical vapor deposition of sufficient thickness to fill the cavity of said trench but deposited under selective deposition conditions favoring the deposition on the exposed surface of said trench but not on any other surface protected with a dielectric film.

Claim 59

A structure as in claim 47 wherein said low resistivity trench connector is held at a supply voltage, thereby forming an impenetrable barrier to minority carriers generated in the bulk of said semiconductor material of first conductivity type.

Claim 60

A trench interconnection structure comprising: a layer of semiconductor material having a top surface, said layer formed of semiconductor material of first conductivity type; a buried region spaced apart from said top surface of said layer of semiconductor material; a trench having an aperture at said top surface of said layer of semiconductor material and also having essentially vertical sidewalls extending into said layer of semiconductor material and into said buried region; interconnect material formed in a layer covering said sidewalls of said trench and having a top surface near the said top surface of said layer of semiconductor material, said interconnect material forming a vertical trench electrical interconnection between said top surface of said interconnect material and said buried region; and a filler material within the portion of said trench not covered by said interconnect material, wherein said interconnect material is heavily doped so as to reduce the electrical resistance between said top surface of said interconnect material and said buried region to within the range of approximately 50 and 10 4 ohms.

Claim 61

A trench interconnection structure comprising: a layer of semiconductor material having a top surface, said layer formed of semiconductor material of first conductivity type; a buried region spaced apart from said top surface of said layer of semiconductor material; a trench having an aperture at said top surface of said layer of semiconductor material and also having essentially vertical sidewalls extending into said layer of semiconductor material and into said buried region; interconnect material formed in a layer covering said sidewalls of said trench and having a top surface near the said top surface of said layer of semiconductor material, said interconnect material forming a vertical trench electrical interconnection between said top surface of said interconnect material and said buried region; and a filler material within the portion of said trench not covered by said interconnect material, wherein said interconnect material is heavily doped so as to reduce the electrical resistance between said top surface of said interconnect material and said buried region to within the range of approximately 50 and 10 4 ohms.

Claim 62

A trench interconnection structure comprising: a layer of semiconductor material having a top surface, said layer formed of semiconductor material of first conductivity type; a buried region spaced apart from said top surface of said layer of semiconductor material; a trench having an aperture at said top surface of said layer of semiconductor material and also having essentially vertical sidewalls extending into said layer of semiconductor material and into said buried region; interconnect material formed in a layer covering said sidewalls of said trench and having a top surface near said top surface of said layer of semiconductor material, said interconnect material forming a vertical trench electrical interconnection between said top surface of said interconnect material and said buried region; and a filler material within the portion of said trench not covered by said interconnect material wherein said interconnect material comprises a low resistivity material, thereby providing an electrical resistance between said top surface of said interconnect material and said buried region of less than approximately 10 ohms.

Claim 63

A trench interconnection structure comprising: a layer of semiconductor material having a top surface, said layer formed of semiconductor material of first conductivity type; a buried region spaced apart from said top surface of said layer of semiconductor material; a trench having an aperture at said top surface of said layer of semiconductor material and also having essentially vertical sidewalls extending into said layer of semiconductor material and into said buried region; interconnect material formed in a layer covering said sidewalls of said trench and having a top surface near said top surface of said layer of semiconductor material, said interconnect material forming a vertical trench electrical interconnection between said top surface of said interconnect material and said buried region; and a filler material within the portion of said trench not covered by said interconnect material wherein said interconnect material comprises a low resistivity material, thereby providing an electrical resistance between said top surface of said interconnect material and said buried region of less than approximately 10 ohms.

Claim 64

A trench interconnection structure comprising: a layer of semiconductor material having a top surface, said layer formed of semiconductor material of first conductivity type; a buried region spaced apart from said top surface of said layer of semiconductor material; a trench having an aperture at said top surface of said layer semiconductor material and also having essentially vertical sidewalls extending into said layer of semiconductor material and into said buried region; interconnect material formed in a layer covering said sidewalls of said trench and having a top surface near said top surface of said layer of semiconductor material, said interconnect material forming a vertical trench electrical interconnection between said top surface of said interconnect material and said buried region; and a filler material within the portion of said trench not covered by said interconnect material wherein said interconnect material comprises a low resistivity material.

Claim 65

A trench interconnection structure comprising: a layer of semiconductor material having a top surface, said layer formed of semiconductor material of first conductivity type; a buried region spaced apart from said top surface of said layer of semiconductor material; a trench having an aperture at said top surface of said layer semiconductor material and also having essentially vertical sidewalls extending into said layer of semiconductor material and into said buried region; interconnect material formed in a layer covering said sidewalls of said trench and having a top surface near said top surface of said layer of semiconductor material, said interconnect material forming a vertical trench electrical interconnection between said top surface of said interconnect material and said buried region; and a filler material within the portion of said trench not covered by said interconnect material wherein said interconnect material comprises a low resistivity material.

Claim 66

A trench interconnection structure comprising: a layer of semiconductor material having a top surface, said layer formed of semiconductor material of first conductivity type; a buried region spaced apart from said top surface of said layer of semiconductor material; a trench having an aperture at said top surface of said layer of semiconductor material and also having essentially vertical sidewalls extending into said layer of semiconductor material and into said buried region; interconnect material formed in a layer covering said sidewalls of said trench and having a top surface near said top surface of said layer of semiconductor material, said interconnect material forming a vertical trench electrical interconnection between said top surface of said interconnect material and said buried region; and a filler material within the portion of said trench not covered by said interconnect material wherein said interconnect material comprises tungsten silicide or tungsten formed by low pressure chemical vapor deposition of sufficient thickness to fill the cavity of said trench but deposited under selective deposition conditions favoring the deposition on the exposed surface at said bottom of said trench but not on any other surface protected with a dielectric film.

Claim 67

A trench interconnection structure comprising: a layer of semiconductor material having a top surface, said layer formed of semiconductor material of first conductivity type; a buried region spaced apart from said top surface of said layer of semiconductor material; a trench having an aperture at said top surface of said layer of semiconductor material and also having essentially vertical sidewalls extending into said layer of semiconductor material and into said buried region; interconnect material formed in a layer covering said sidewalls of said trench and having a top surface near said top surface of said layer of semiconductor material, said interconnect material forming a vertical trench electrical interconnection between said top surface of said interconnect material and said buried region; and a filler material within the portion of said trench not covered by said interconnect material wherein said interconnect material comprises tungsten silicide or tungsten formed by low pressure chemical vapor deposition of sufficient thickness to fill the cavity of said trench but deposited under selective deposition conditions favoring the deposition on the exposed surface at said bottom of said trench but not on any other surface protected with a dielectric film.

Claim 68

A trench interconnection structure as in claim 44 wherein said interconnect material is formed in a layer covering said sidewalls of said trench, further comprising a filler material within the portion of said trench not covered by said interconnect material.

Claim 69

A trench interconnection structure as in claim 55 wherein said filler material has a higher resistivity than said interconnect material.

Claim 70

A trench interconnection structure as in claim 56 wherein said interconnect material comprises undoped polycrystalline silicon, doped polycrystalline silicon, or polycrystalline silicide, and said filler material comprises doped polycrystalline silicon, undoped polycrystalline silicon, silicon dioxide, or silicon nitride.

Claim 71

A trench interconnection structure as in claim 47 wherein said interconnect material is formed in a layer covering said sidewalls of said trench, further comprising a filler material within the portion of said trench not covered by said interconnect material.

Claim 72

A trench interconnection structure as in claim 58 wherein said filler material has a higher resistivity than said interconnect material.

Claim 73

A trench interconnection structure as in claim 59 wherein said interconnect material comprises undoped polycrystalline silicon, doped polycrystalline silicon, or polycrystalline silicide, and said filler material comprises doped polycrystalline silicon, undoped polycrystalline silicon, silicon dioxide, or silicon nitride.

Claim 74

A structure as in claim 21 wherein said interconnect material comprises policide, silicide, or refractory metal, and said filler material comprises doped polycrystalline silicon, undoped polycrystalline silicon, silicon dioxide, or silicon nitride.

Claim 75

A structure as in claim 56 wherein said interconnect material comprises policide, silicide, or refractory metal.

Claim 76

A structure as in claim 61 wherein said interconnect material comprises policide, silicide, or refractory metal.

Claim 77

A structure as in claim 62 wherein said interconnect material comprises policide, silicide or refractory metal, and said filler material comprises doped polycrystalline silicon, undoped polycrystalline silicon, silicon dioxide, or silicon nitride.