US4569122A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of forming a low resistance quasi-buried contact
Assignee: Advanced Micro Devices Inc
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Filing: 1983-03-09
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Granted: 1986-02-11
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Expires: 2003-03-09
Abstract
Abstract A fabrication method and resulting integrated circuit structure that provide a second level of interconnect, a low resistance contact strap between underlying layers which is not sensitive to alignment and low lateral diffusion polysilicon load. The method comprises the steps of providing contact openings in an insulating layer on a wafer to any desired underlying circuit layers, depositing a silicide layer on the wafer, removing selected portions of the silicide layer, depositing a polysilicon layer on the wafer, lightly doping the polysilicon layer to a level appropriate for the resistor, and then removing portions of the polysilicon along with underlying silicide.
Inventors
- 👤 Hugo W. K. Chan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 12:33
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D64/663; H10D1/00; H10D1/40; H10D1/47; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/066; H10W20/071; H10W20/074; H10W20/077; H10W20/40; H10W20/41; H10W20/44; H10W20/4451; H10B; H10B10/00; H10B10/15; Y; Y10; Y10S; Y10S257/00; Y10S257/903; Y10S257/904
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
109 words
In the fabrication of an integrated circuit structure on a semiconductor substrate, a method of forming a low resistance quasi-buried contact between a first polycrystalline layer and a heavily doped region of said substrate, comprising the steps of: depositing a silicide layer over a contiguious region between said first polycrystalline layer and said substrate region and extending there beyond to overlap said first polycrystalline layer and said substrate region; and depositing a polycrystalline silicon layer over said silicide layer; whereupon a low resistance interconnection is provided between said first polycrystalline layer and said substrate region, regardless of the overlap distance between said first polycrystalline layer and said substrate region.
Claim 2
Dependent Claim
109 words
In the fabrication of an integrated circuit structure on a semiconductor substrate, a method of forming a low resistance quasi-buried contact between a first polycrystalline layer and a heavily doped region of said substrate, comprising the steps of: depositing a silicide layer over a contiguious region between said first polycrystalline layer and said substrate region and extending there beyond to overlap said first polycrystalline layer and said substrate region; and depositing a polycrystalline silicon layer over said silicide layer; whereupon a low resistance interconnection is provided between said first polycrystalline layer and said substrate region, regardless of the overlap distance between said first polycrystalline layer and said substrate region.
Claim 3
Dependent Claim
23 words
The invention of claim 1, and further comprising the step of doping said polycrystalline layer to determine the conductivity of said resistor portions.
Claim 4
Dependent Claim
27 words
The invention of claim 1, and further comprising the step, carried out prior to said step of depositing a silicide layer, of depositing a polycrystalline buffer layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-02-10 | 1989-08-12 | 1990-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-02-10 | 1993-08-12 | 1994-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-02-10 | 1997-08-12 | 1998-02-11 | $7700.00 | Window Closed / Lapsed |