US4419812A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating an integrated circuit voltage multiplier containing a parallel plate capacitor
Assignee: NCR Voyix Corp
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Filing: 1982-08-23
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Granted: 1983-12-13
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Expires: 2002-08-23
Abstract
Abstract Disclosed is a process which is fully compatible with normal two layer polysilicon SNOS process and provides polysilicon parallel plate capacitors and silicon gate non-memory MOS transistors (diodes) for constructing therefrom an on-chip, dual polarity high voltage multiplier. From the polysilicon I layer deposited over a gate oxide, the polysilicon I resistor, the non-memory device gate and the capacitor lower plate are formed. Then, the resistor, non-memory device gate and active region and the periphery of the capacitor lower plate are covered with an isolation oxide. Next, a dielectric, e.g., oxide-nitride, and polysilicon II layers are formed over the structure. Polysilicon II is patterned into interconnect, gate for SNOS memory device and capacitor upper plate, the latter having a plurality of holes therein. The dielectric is formed into SNOS device gate insulator and the capacitor insulator, the latter having holes in registration with the holes in the capacitor upper plate. Finally, by thermal diffusion of active impurities, all gates, interconnect and both capacitor plates are doped and all sources and drains for memory and non-memory devices formed.
Inventors
- 👤 James A. Topich
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 17:46
CPC Classifications
H; H10; H10P; H10P95/00; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/06; H02M3/07; H02M3/073; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/00; H10D88/01; Y; Y10; Y10T; Y10T29/00; Y10T29/43; Y10T29/435
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
96 words
A process for forming a parallel conductive plate capacitor on a semiconductive substrate comprising: forming a first plate over said substrate; forming a dielectric layer over said first plate; forming a second plate having a plurality of windows over said dielectric; forming windows in said dielectric layer in a corresponding relationship with the windows in said second plate thereby forming a structure in which portions of the first plate which are in correspondence with said windows in the dielectric layer are exposed; and subjecting the structure to a doping step to dope the entire first plate.
Claim 2
Dependent Claim
96 words
A process for forming a parallel conductive plate capacitor on a semiconductive substrate comprising: forming a first plate over said substrate; forming a dielectric layer over said first plate; forming a second plate having a plurality of windows over said dielectric; forming windows in said dielectric layer in a corresponding relationship with the windows in said second plate thereby forming a structure in which portions of the first plate which are in correspondence with said windows in the dielectric layer are exposed; and subjecting the structure to a doping step to dope the entire first plate.
Claim 3
Dependent Claim
32 words
The process as in claim 1 wherein said first plate is made of polycrystalline silicon and said second plate is made of either a metal or a refractory metal silicide or polycide.
Claim 4
Dependent Claim
57 words
The process as in claim 1 wherein said first and second plates are made of polycrystalline silicon and said process including doping said second plate simultaneously with doping of the first plate by depositing a dopant-bearing material over said second plate and the exposed portions of the first plate and thermally diffusing said dopant into said plates.
Claim 5
Dependent Claim
144 words
A process for forming a parallel conductive polysilicon plate capacitor on a semiconductive substrate comprising the steps in the sequence set forth: forming a first polysilicon plate over said substrate; forming a dielectric layer over said first polysilicon plate; forming a second polysilicon plate having a plurality of windows of a predetermined size and relative separation; forming windows in said dielectric layer in correspondence with the windows in said second plate thereby exposing portions of said first plate which are in registry with said windows in the dielectric layer; doping said first and second plates simultaneously by depositing a dopant-bearing material over said second plate and the exposed portions of the first plate and by controlled thermal diffusion laterally diffusing the dopant from said dopant-bearing material into said first and second plates; whereby the entire first plate is doped to a uniform doping level.
Claim 6
Dependent Claim
144 words
A process for forming a parallel conductive polysilicon plate capacitor on a semiconductive substrate comprising the steps in the sequence set forth: forming a first polysilicon plate over said substrate; forming a dielectric layer over said first polysilicon plate; forming a second polysilicon plate having a plurality of windows of a predetermined size and relative separation; forming windows in said dielectric layer in correspondence with the windows in said second plate thereby exposing portions of said first plate which are in registry with said windows in the dielectric layer; doping said first and second plates simultaneously by depositing a dopant-bearing material over said second plate and the exposed portions of the first plate and by controlled thermal diffusion laterally diffusing the dopant from said dopant-bearing material into said first and second plates; whereby the entire first plate is doped to a uniform doping level.
Claim 7
Dependent Claim
15 words
The process as recited in claims 3 or 4 wherein said dielectric is silicon nitride.
Claim 8
Dependent Claim
30 words
The process as recited in claim 4 wherein said controlled thermal diffusion includes adjusting the diffusion temperature and time to dope the entire first plate to a uniform conductivity level.
Claim 9
Dependent Claim
41 words
The process as in claim 6 wherein said windows are 3 microns square in size, said relative window separation is 4.25 microns, said dopant is phosphorus, the diffusion temperature is approximately 900° C. and the diffusion time is about 2 hours.
Claim 10
Dependent Claim
234 words
A process for forming a conductive polysilicon parallel plate capacitor and a polysilicon gate enhancement mode transistor for a voltage multiplier on a semiconductive substrate of a first conductivity type having an active region of a second conductivity type and a field isolation oxide region, said process comprising: forming a gate oxide layer over said active region; doping said active region to adjust the threshold voltage; forming a first polysilicon layer over said gate oxide; patterning said first polysilicon layer into a transistor gate electrode corresponding to said active region and a first plate of the capacitor corresponding to said field oxide region; forming an isolation oxide layer over said structure; selectively removing the isolation oxide over a central portion of the first polysilicon capacitor plate; forming a dielectric layer over the structure; forming a second polysilicon layer over said dielectric layer; patterning said second polysilicon into the second capacitor plate having a plurality of holes therein; patterning said dielectric layer into the capacitor insulator having a plurality of holes in correspondence with the holes in said second polysilicon capacitor plate; removing said isolation oxide to expose said gate electrode and said active region; and thermally diffusing or ion implanting active impurities of the first conductivity type to dope said first and second polysilicon capacitor plates and said gate electrode and form a source and a drain in self-aligned relationship with said gate electrode.
Claim 11
Dependent Claim
234 words
A process for forming a conductive polysilicon parallel plate capacitor and a polysilicon gate enhancement mode transistor for a voltage multiplier on a semiconductive substrate of a first conductivity type having an active region of a second conductivity type and a field isolation oxide region, said process comprising: forming a gate oxide layer over said active region; doping said active region to adjust the threshold voltage; forming a first polysilicon layer over said gate oxide; patterning said first polysilicon layer into a transistor gate electrode corresponding to said active region and a first plate of the capacitor corresponding to said field oxide region; forming an isolation oxide layer over said structure; selectively removing the isolation oxide over a central portion of the first polysilicon capacitor plate; forming a dielectric layer over the structure; forming a second polysilicon layer over said dielectric layer; patterning said second polysilicon into the second capacitor plate having a plurality of holes therein; patterning said dielectric layer into the capacitor insulator having a plurality of holes in correspondence with the holes in said second polysilicon capacitor plate; removing said isolation oxide to expose said gate electrode and said active region; and thermally diffusing or ion implanting active impurities of the first conductivity type to dope said first and second polysilicon capacitor plates and said gate electrode and form a source and a drain in self-aligned relationship with said gate electrode.
Claim 12
Dependent Claim
11 words
The process of claim 8 wherein said dielectric is silicon nitride.
Claim 13
Independent Claim
278 words
A method of forming a monolithic integrated circuit comprising a polysilicon gate memory field-effect transistor, a polysilicon resistive element, a polysilicon gate non-memory depletion mode field-effect transistor and a parallel polysilicon plate capacitor, said non-memory transistor and capacitor being suitable for on-chip voltage multiplier connection, with a substrate of a first conductivity type having first and second active regions of a second conductivity type and a field isolation oxide region, said process comprising the steps of: forming a gate oxide layer over said substrate; forming over said gate oxide layer a doped first polysilicon layer suitable for forming resistive elements therefrom; patterning the first polysilicon layer into a non-memory device gate electrode corresponding to said first active region, a resistive element and the first plate of the capacitor corresponding to said field isolation oxide region; forming an isolation oxide layer over the resistive element, the first active region including said gate electrode and around the periphery of the first capacitor plate; forming a dielectric over said structure; forming a second polysilicon layer over said dielectric; patterning said second polysilicon layer into a gate for the memory device corresponding to said second active region and a second capacitor plate having a plurality of holes therein; patterning said dielectric into a gate dielectric for said memory device and the capacitor insulator having thereon holes in correspondence with the holes in said second polysilicon plate; removing said isolation oxide to expose said non-memory device gate electrode and active region; and thermally diffusing active impurities of the first conductivity type to dope said first and second capacitor plates, said gate electrodes and form sources and drains in self-aligned relationship with said gates.
Claim 14
Independent Claim
278 words
A method of forming a monolithic integrated circuit comprising a polysilicon gate memory field-effect transistor, a polysilicon resistive element, a polysilicon gate non-memory depletion mode field-effect transistor and a parallel polysilicon plate capacitor, said non-memory transistor and capacitor being suitable for on-chip voltage multiplier connection, with a substrate of a first conductivity type having first and second active regions of a second conductivity type and a field isolation oxide region, said process comprising the steps of: forming a gate oxide layer over said substrate; forming over said gate oxide layer a doped first polysilicon layer suitable for forming resistive elements therefrom; patterning the first polysilicon layer into a non-memory device gate electrode corresponding to said first active region, a resistive element and the first plate of the capacitor corresponding to said field isolation oxide region; forming an isolation oxide layer over the resistive element, the first active region including said gate electrode and around the periphery of the first capacitor plate; forming a dielectric over said structure; forming a second polysilicon layer over said dielectric; patterning said second polysilicon layer into a gate for the memory device corresponding to said second active region and a second capacitor plate having a plurality of holes therein; patterning said dielectric into a gate dielectric for said memory device and the capacitor insulator having thereon holes in correspondence with the holes in said second polysilicon plate; removing said isolation oxide to expose said non-memory device gate electrode and active region; and thermally diffusing active impurities of the first conductivity type to dope said first and second capacitor plates, said gate electrodes and form sources and drains in self-aligned relationship with said gates.
Claim 15
Dependent Claim
35 words
The process of claim 10 further including patterning said second polysilicon layer in said second polysilicon patterning step into an interconnect corresponding to said resistive element and doping said interconnect during said thermal diffusion step.
Claim 16
Dependent Claim
25 words
The process as in claim 8, 10 or 11 wherein said dielectric is a dual layer of a relatively thin silicon dioxide and silicon nitride.
Claim 17
Dependent Claim
25 words
The process as in claim 8, 10 or 11 wherein said dielectric is a dual layer of a relatively thin silicon dioxide and silicon oxynitride.
Claim 18
Dependent Claim
27 words
The process as in claim 8, 10 or 11 wherein said dielectric is a triple layer of silicon dioxide, silicon oxynitride and silicon nitride, in that order.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-12-12 | 1987-06-13 | 1987-12-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-12-12 | 1991-06-13 | 1991-12-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-12-12 | 1995-06-13 | 1995-12-13 | $7700.00 | Window Closed / Lapsed |