Highly compact eprom and flash eeprom divices

Claim 1

A method of forming a split-channel electrically programmable read only memory transistor on a semiconductor substrate surface, comprising the steps of: forming on said surface a floating gate having sidewalls and being electrically isolated by a gate dielectric layer from said substrate, forming a spacer immediately adjacent only one sidewall of said floating gate and extending a controlled distance over said substrate surface, forming source and drain regions in said substrate by using said floating gate and said spacer as a mask, whereby a channel region is formed in the substrate under the masked region between the source and drain regions, removing said spacer, and forming a control gate extending over at least a portion of the floating gate and substrate channel region that was occupied by said spacer, said control gate being electrically insulated from said floating gate and said substrate, whereby a split-channel electrically programmable read only memory transistor is formed.

Claim 2

A method of forming a split-channel electrically programmable read only memory transistor on a semiconductor substrate surface, comprising the steps of: forming on said surface a floating gate having sidewalls and being electrically isolated by a gate dielectric layer from said substrate, forming a spacer immediately adjacent only one sidewall of said floating gate and extending a controlled distance over said substrate surface, forming source and drain regions in said substrate by using said floating gate and said spacer as a mask, whereby a channel region is formed in the substrate under the masked region between the source and drain regions, removing said spacer, and forming a control gate extending over at least a portion of the floating gate and substrate channel region that was occupied by said spacer, said control gate being electrically insulated from said floating gate and said substrate, whereby a split-channel electrically programmable read only memory transistor is formed.

Claim 9

A method of forming a split-channel flash electrically erasable and programmable read only memory transistor on a semiconductor substrate surface, comprising the steps of: forming on said surface a floating gate having opposite sides and opposite ends, said floating gate being electrically insulated from said substrate by a gate dielectric layer, forming in said substrate a drain region adjacent one side of said floating gate and a source region spaced apart from an opposite side of said floating gate, thereby to form a channel region between the source and drain that has a first channel region under the floating gate and a second channel region between the source region and the opposite floating gate side, forming a control gate extending over at least a portion of the floating gate and said second channel region, said control gate being electrically insulated from said floating gate and said substrate, forming regions of a tunnel erase dielectric layer on each of opposite ends of said floating gate, and forming a pair of parallel erase gates extending over the opposite ends of the floating gate on the tunnel erase dielectric layers.

Claim 10

A method of forming a split-channel flash electrically erasable and programmable read only memory transistor on a semiconductor substrate surface, comprising the steps of: forming on said surface a floating gate having opposite sides and opposite ends, said floating gate being electrically insulated from said substrate by a gate dielectric layer, forming in said substrate a drain region adjacent one side of said floating gate and a source region spaced apart from an opposite side of said floating gate, thereby to form a channel region between the source and drain that has a first channel region under the floating gate and a second channel region between the source region and the opposite floating gate side, forming a control gate extending over at least a portion of the floating gate and said second channel region, said control gate being electrically insulated from said floating gate and said substrate, forming regions of a tunnel erase dielectric layer on each of opposite ends of said floating gate, and forming a pair of parallel erase gates extending over the opposite ends of the floating gate on the tunnel erase dielectric layers.

Claim 12

A method of forming a split channel flash electrically erasable and programmable read only memory transistor on a semiconductor substrate surface, comprising the steps of: forming a first layer of thin silicon dioxide covered by silicon nitride as an oxidation inhibiting mask, forming a second layer of dielectric material over said first layer, said second layer being etchable by a given etching process while said first layer is not, forming over the second layer a masking layer that has at least two spaced apart openings, removing exposed portions of said second layer by said given process, including removal of said second layer under the masking layer by sideway etching for a predetermined distance from each edge of said masking layer at said openings, implanting source and drain regions in said substrate through said spaced apart openings, said masking layer serving to protect from such implant a channel region in said substrate between the source and drain regions, removing exposed regions of said silicon nitride overlying said source and drain regions, removing said masking layer, forming an isolation oxide layer over said source and drain regions and over any parts of said substrate surface which is not covered by said oxidation inhibiting mask, implanting dopant in the channel region adjacent to the drain region by using the remaining portion of said second layer as a mask for one edge of a heavily doped channel region extending from said drain by said predetermined distance towards said source but not extending all the way to said source, stripping the remaining part of said second layer and said first layer but not completely removing said isolation oxide layer, forming a thin gate dielectric oxide film over said channel, forming a floating gate over said heavily doped channel region and extending in a first direction a distance on either side thereof but remaining spaced apart from said source region, said floating gate having a finite extent in a second direction orthogonal to said first direction that terminates in opposite ends thereof, forming a control gate over the floating gate and over a portion of the channel region adjacent the source region that is not covered by the floating gate, and forming a pair of erase gates which overlap at least one of the opposite ends of said floating gate and separated therefrom by a tunnel erase dielectric film, said erase gates being formed to be insulated from said control gate and said substrate surface.

Claim 13

A method of forming a split channel flash electrically erasable and programmable read only memory transistor on a semiconductor substrate surface, comprising the steps of: forming a first layer of thin silicon dioxide covered by silicon nitride as an oxidation inhibiting mask, forming a second layer of dielectric material over said first layer, said second layer being etchable by a given etching process while said first layer is not, forming over the second layer a masking layer that has at least two spaced apart openings, removing exposed portions of said second layer by said given process, including removal of said second layer under the masking layer by sideway etching for a predetermined distance from each edge of said masking layer at said openings, implanting source and drain regions in said substrate through said spaced apart openings, said masking layer serving to protect from such implant a channel region in said substrate between the source and drain regions, removing exposed regions of said silicon nitride overlying said source and drain regions, removing said masking layer, forming an isolation oxide layer over said source and drain regions and over any parts of said substrate surface which is not covered by said oxidation inhibiting mask, implanting dopant in the channel region adjacent to the drain region by using the remaining portion of said second layer as a mask for one edge of a heavily doped channel region extending from said drain by said predetermined distance towards said source but not extending all the way to said source, stripping the remaining part of said second layer and said first layer but not completely removing said isolation oxide layer, forming a thin gate dielectric oxide film over said channel, forming a floating gate over said heavily doped channel region and extending in a first direction a distance on either side thereof but remaining spaced apart from said source region, said floating gate having a finite extent in a second direction orthogonal to said first direction that terminates in opposite ends thereof, forming a control gate over the floating gate and over a portion of the channel region adjacent the source region that is not covered by the floating gate, and forming a pair of erase gates which overlap at least one of the opposite ends of said floating gate and separated therefrom by a tunnel erase dielectric film, said erase gates being formed to be insulated from said control gate and said substrate surface.

Claim 27

A method of forming a two dimensional array of flash electrically erasable and programmable read only memory cells on a semiconductor substrate, comprising the steps of: forming on said substrate a plurality of rectangularly shaped floating gates in a two dimensional array of symmetrical rows and columns by use of a first photolithography mask, each floating gate being isolated from said substrate by a gate dielectric layer and having opposing end walls separated by a first distance, forming source and drain regions in said substrate by using the plurality of floating gates as a portion of another mask to define a channel between the source and drain regions, forming a tunnel erase dielectric layer on the floating gates in regions adjacent their ends, forming a plurality of control gates that each extend over several of the floating gates with insulation therebetween, and forming on said substrate with a second photolithography mask separate from said first mask a plurality of elongated parallel erase gates separated by a second distance and positioned between rows of floating gates with a width sufficient to contact said erase dielectric regions on the floating gates thereof.

Claim 28

A method of forming a two dimensional array of flash electrically erasable and programmable read only memory cells on a semiconductor substrate, comprising the steps of: forming on said substrate a plurality of rectangularly shaped floating gates in a two dimensional array of symmetrical rows and columns by use of a first photolithography mask, each floating gate being isolated from said substrate by a gate dielectric layer and having opposing end walls separated by a first distance, forming source and drain regions in said substrate by using the plurality of floating gates as a portion of another mask to define a channel between the source and drain regions, forming a tunnel erase dielectric layer on the floating gates in regions adjacent their ends, forming a plurality of control gates that each extend over several of the floating gates with insulation therebetween, and forming on said substrate with a second photolithography mask separate from said first mask a plurality of elongated parallel erase gates separated by a second distance and positioned between rows of floating gates with a width sufficient to contact said erase dielectric regions on the floating gates thereof.

Claim 31

A method of forming a two dimensional array of flash electrically erasable and programmable read only memory cells on a semiconductor substrate surface, comprising the steps of: forming a first layer of thin silicon dioxide covered by silicon nitride as an oxidation inhibiting mask, forming a second layer of dielectric material over said first layer, said second layer being etchable by a given etching process while said first layer is not, forming over the second layer a masking layer that includes a plurality of openings elongated in a first direction and spaced apart in a second direction that is substantially orthogonal to said first direction, said openings being positioned at locations where elongated source and drain regions are desired to be formed, removing exposed portions of said second layer by said given etching process, including removal of said second layer under the masking layer by sideway etching a predetermined distance from each edge of said masking layer at said openings, implanting through said openings alternate source and drain regions in said substrate elongated in said first direction thereacross, said masking layer serving to protect from such implant channel regions in said substrate between adjacent ones of the source and drain regions, removing exposed regions of said silicon nitride overlying said source and drain regions, removing said masking layer, forming an isolation oxide layer over said source and drain regions as well as over any parts of said substrate surface which is not covered by said oxidation inhibiting mask, including regions of isolation between adjacent memory cells, implanting dopant in the channel regions adjacent to said drain regions by using the remaining portion of said second layer as a mask for one edge and said isolation oxide layer over said drain as a mask for a second edge of heavily doped channel regions extending from said drain regions by said predetermined distance towards said source regions but not extending all the way to said source regions, stripping the remaining part of said second layer and said first layer but not completely remvoing said isolation oxide layer, forming a thin gate dielectric oxide film over said channel regions, forming a plurality of floating gates is a first conductive layer on said gate dielectric oxide film, each floating gate overlying a corresponding one of said heavily doped channel regions and extending a distance on either side thereof, but not overlying the second channel portion adjacent to the corresponding one of said source regions, forming a second dielectric layer on said first conductive layer and said substrate, forming in a second conductive layer a plurality of control gate strips elongated in said second direction, each control gate strip extending over several of said floating gates and said second channel portions, forming an insulating film over said control gate strips, removing said second dielectric layer in exposed areas between adjacent ones of said control gate strips, forming a tunnel erase dielectric film on the exposed surfaces of said floating gates at their opposing ends that are not covered by said control gate strips, and forming in a third conductive layer a plurality of erase gate strips elongated in said second direction and positioned over said substrate surface inbetween adjacent ones of said control gate strips, in a manner to overlap at least one of opposing ends of each of said floating gates in the row of memory cells positioned inbetween said adjacent pair of erase gate strips.

Claim 32

A method of forming a two dimensional array of flash electrically erasable and programmable read only memory cells on a semiconductor substrate surface, comprising the steps of: forming a first layer of thin silicon dioxide covered by silicon nitride as an oxidation inhibiting mask, forming a second layer of dielectric material over said first layer, said second layer being etchable by a given etching process while said first layer is not, forming over the second layer a masking layer that includes a plurality of openings elongated in a first direction and spaced apart in a second direction that is substantially orthogonal to said first direction, said openings being positioned at locations where elongated source and drain regions are desired to be formed, removing exposed portions of said second layer by said given etching process, including removal of said second layer under the masking layer by sideway etching a predetermined distance from each edge of said masking layer at said openings, implanting through said openings alternate source and drain regions in said substrate elongated in said first direction thereacross, said masking layer serving to protect from such implant channel regions in said substrate between adjacent ones of the source and drain regions, removing exposed regions of said silicon nitride overlying said source and drain regions, removing said masking layer, forming an isolation oxide layer over said source and drain regions as well as over any parts of said substrate surface which is not covered by said oxidation inhibiting mask, including regions of isolation between adjacent memory cells, implanting dopant in the channel regions adjacent to said drain regions by using the remaining portion of said second layer as a mask for one edge and said isolation oxide layer over said drain as a mask for a second edge of heavily doped channel regions extending from said drain regions by said predetermined distance towards said source regions but not extending all the way to said source regions, stripping the remaining part of said second layer and said first layer but not completely remvoing said isolation oxide layer, forming a thin gate dielectric oxide film over said channel regions, forming a plurality of floating gates is a first conductive layer on said gate dielectric oxide film, each floating gate overlying a corresponding one of said heavily doped channel regions and extending a distance on either side thereof, but not overlying the second channel portion adjacent to the corresponding one of said source regions, forming a second dielectric layer on said first conductive layer and said substrate, forming in a second conductive layer a plurality of control gate strips elongated in said second direction, each control gate strip extending over several of said floating gates and said second channel portions, forming an insulating film over said control gate strips, removing said second dielectric layer in exposed areas between adjacent ones of said control gate strips, forming a tunnel erase dielectric film on the exposed surfaces of said floating gates at their opposing ends that are not covered by said control gate strips, and forming in a third conductive layer a plurality of erase gate strips elongated in said second direction and positioned over said substrate surface inbetween adjacent ones of said control gate strips, in a manner to overlap at least one of opposing ends of each of said floating gates in the row of memory cells positioned inbetween said adjacent pair of erase gate strips.

Claim 33

A method of forming a two dimensional array of flash electrically erasable and programmable read only memory cells on a semiconductor substrate, comprising the steps of: forming on said substrate a plurality of rectangularly shaped floating gates, each floating gate having opposing sides and opposing ends separated by a first distance, forming source and drain regions in said substrate by using the plurality of floating gates as a portion of another mask to define a channel between the source and drain regions, placing a tunnel dielectric layer on the floating gates between their opposing sides intermediate of their opposing ends, forming a plurality of elongated erase gates that each extend across several of the floating gates over the tunnel dielectric thereon, said erase gates having a width significantly less than said first distance, and forming a plurality of elongated control gates coextensive with said erase gates and insulated therefrom, a control gate being formed over and around a floating gate and having a width that is significantly greater than that of said erase gate.

Claim 34

A method of forming a two dimensional array of flash electrically erasable and programmable read only memory cells on a semiconductor substrate, comprising the steps of: forming on said substrate a plurality of rectangularly shaped floating gates, each floating gate having opposing sides and opposing ends separated by a first distance, forming source and drain regions in said substrate by using the plurality of floating gates as a portion of another mask to define a channel between the source and drain regions, placing a tunnel dielectric layer on the floating gates between their opposing sides intermediate of their opposing ends, forming a plurality of elongated erase gates that each extend across several of the floating gates over the tunnel dielectric thereon, said erase gates having a width significantly less than said first distance, and forming a plurality of elongated control gates coextensive with said erase gates and insulated therefrom, a control gate being formed over and around a floating gate and having a width that is significantly greater than that of said erase gate.

Claim 35

A method of forming a two dimensional array of symmetrical rows and columns of flash electrically erasable and programmable read only memory cells on a semiconductor substrate, comprising the steps of: forming on said substrate a gate dielectric layer, forming on said gate dielectric layer by a first mask a plurality of parallel narrow elongated strips in a first conductive layer with their lengths extending in a first direction, forming source and drain regions in said substrate in elongated narrow strips with their lengths extending in said first direction by using said narrow strips as a portion of a second mask to define channels between said source and drain regions, wherein each such channel between a corresponding one of said source and said drain regions has a first channel portion adjacent to said drain region which is covered by a corresponding one of said narrow strips and a second channel portion adjacent to said source region which is not covered by said narrow strip but adjacent thereto, forming a second dielectric layer on said first conductive layer and said substrate, forming with a third mask in a second conductive layer over said second dielectric layer a plurality of parallel strips of elongated control gates having a given width and their lengths extending in a second direction orthogonal to said first direction, thereby to form each control gate extending over several of said narrow strips and said second channel portions, forming an insulating film over said control gate strips, removing said second dielectric layer in exposed areas between adjacent strips of said control gates, removing said narrow strips of said first conductive layer in exposed areas where said second dielectric layer has been removed, thereby forming said first conductive layer into individual floating gates whose opposing ends are essentially self-aligned with the edges of said strips of control gates, forming a tunnel erase dielectric on the exposed vertical sidewalls of said opposing ends of said floating gates, and forming with a fourth mask in a third conductive layer a plurality of parallel strips of erase gates in said second direction and overlying said substrate between adjacent rows of floating gates and having a strip to strip separation less than said given width so as to overlie said tunnel erase dielectric on said opposing ends of said floating gates.

Claim 36

A method of forming a two dimensional array of symmetrical rows and columns of flash electrically erasable and programmable read only memory cells on a semiconductor substrate, comprising the steps of: forming on said substrate a gate dielectric layer, forming on said gate dielectric layer by a first mask a plurality of parallel narrow elongated strips in a first conductive layer with their lengths extending in a first direction, forming source and drain regions in said substrate in elongated narrow strips with their lengths extending in said first direction by using said narrow strips as a portion of a second mask to define channels between said source and drain regions, wherein each such channel between a corresponding one of said source and said drain regions has a first channel portion adjacent to said drain region which is covered by a corresponding one of said narrow strips and a second channel portion adjacent to said source region which is not covered by said narrow strip but adjacent thereto, forming a second dielectric layer on said first conductive layer and said substrate, forming with a third mask in a second conductive layer over said second dielectric layer a plurality of parallel strips of elongated control gates having a given width and their lengths extending in a second direction orthogonal to said first direction, thereby to form each control gate extending over several of said narrow strips and said second channel portions, forming an insulating film over said control gate strips, removing said second dielectric layer in exposed areas between adjacent strips of said control gates, removing said narrow strips of said first conductive layer in exposed areas where said second dielectric layer has been removed, thereby forming said first conductive layer into individual floating gates whose opposing ends are essentially self-aligned with the edges of said strips of control gates, forming a tunnel erase dielectric on the exposed vertical sidewalls of said opposing ends of said floating gates, and forming with a fourth mask in a third conductive layer a plurality of parallel strips of erase gates in said second direction and overlying said substrate between adjacent rows of floating gates and having a strip to strip separation less than said given width so as to overlie said tunnel erase dielectric on said opposing ends of said floating gates.