US4835741A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Frasable electrically programmable read only memory cell using a three dimensional trench floating gate
Assignee: Texas Instruments Inc
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Filing: 1986-06-02
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Granted: 1989-05-30
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Expires: 2006-06-02
Abstract
Abstract An electrically programmable read only memory device formed in a face of a semiconductor substrate which includes a floating gate transistor having a floating gate and a control gate formed at least partially in a trench in the substrate.
Inventors
- 👤 David A. Baglee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 06:22
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
81 words
An electrically programmable read only memory device formed in a face of a semiconductor substrate, comprising a floating gate transistor having a floating gate and a control gate formed at least partially in a trench in said substrate and including a tunnel device coupled to a source of said floating gate transistor and having a floating gate connected to the floating gate of said floating gate transistor and a control gate connected to the control gate of said floating gate transistor.
Claim 2
Dependent Claim
81 words
An electrically programmable read only memory device formed in a face of a semiconductor substrate, comprising a floating gate transistor having a floating gate and a control gate formed at least partially in a trench in said substrate and including a tunnel device coupled to a source of said floating gate transistor and having a floating gate connected to the floating gate of said floating gate transistor and a control gate connected to the control gate of said floating gate transistor.
Claim 3
Dependent Claim
19 words
A device according to claim 1, wherein said substrate is silicon and said floating and control gates are polysilicon.
Claim 4
Dependent Claim
21 words
A device according to claim 2, including a selection transistor formed in said substrate in series with said floating gate transistor.
Claim 5
Dependent Claim
25 words
A device according to claim 2, wherein said substrate is P-type silicon, said and the thickness of said polysilicon gates are each about 0.4 microns.
Claim 6
Dependent Claim
13 words
A device according to claim 2, wherein said polysilicon layers are conformally deposited.
Claim 7
Dependent Claim
28 words
A device according to claim 1, wherein said trench has a substantially rectangular cross section which has a common moat region on at least two opposed ends thereof.
Claim 8
Dependent Claim
36 words
A device according to claim 6, wherein said trench has a width in the range of about 2 to 5 microns, a length of 2 to 5 microns and a depth of 1 to 3 microns.
Claim 9
Dependent Claim
26 words
A device according to claim 2, including a silicon dioxide region between said substrate and said floating gate having a thickness of 100 to 500 Angstroms.
Claim 10
Dependent Claim
12 words
A device according to claim 1, wherein said device is electrically erasable.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-29 | 1992-11-28 | 1993-05-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-29 | 1996-11-28 | 1997-05-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-29 | 2000-11-28 | 2001-05-30 | $7700.00 | Window Closed / Lapsed |