US5991204A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Flash eeprom device employing polysilicon sidewall spacer as an erase gate
Assignee: Individual
•
Filing: 1998-05-05
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Granted: 1999-11-23
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Expires: 2018-05-05
Abstract
Abstract A Flash EEPROM cell employing a sidewall polysilicon spacer as an erase gate. The cell is programmed by source side channel hot electron injection and erased by poly-to-poly tunneling through a poly tunnel oxide between the floating gate and the erase gate. The floating gate is defined by the control gate sidewall spacer which is formed before the floating gate poly self-aligned etch step. The polysilicon sidewall spacer erase gate is formed after growing a poly tunnel oxide on the sidewall of the floating gate poly. Since the poly tunnel oxide thickness is minimized, a fast programming with a low power consumption can be achieved. By using poly-to-poly tunneling erase scheme, a deep source junction is not used and cell size can be significantly reduced. Furthermore, a large sector of cells can be erased simultaneously without a power consumption concern and further Vcc scaling becomes possible.
Inventors
- 👤 Ming-Bing Chang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:18
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; H; H10; H10B; H10B41/00; H10B41/10; H10B41/40; H10B41/42; H10B41/49; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/6891; H10D30/6892
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
260 words
A Flash EEPROM cell structure comprising: a body of semiconductor material having a substrate of a first conductivity type, a source region and a drain region each of a second conductivity type, and a channel region of the first conductivity type extending between the source region and the drain region; a floating gate extending over a portion of the channel region with a thin insulator layer therebetween, the floating gate including one sidewall on one side thereof; a control gate overlying the floating gate with an insulator layer therebetween, so as to form a stack gate, the stack gate located proximately to the source region; and a non-self-aligned select gate insulated from the drain region and the stack gate, the select gate located proximately to the drain region and insulated from the sidewall of the floating gate with a first thin dielectric layer therebetween, and insulated from a sidewall of the control gate with a second thin dielectric layer therebetween, the select gate overlying a portion of the substrate and presenting a select gate channel length substantially along the channel region, the select gate also insulated from the portion of the substrate with a third thin dielectric layer therebetween, wherein the first thin dielectric layer is thinner than the second thin dielectric layer such that with proper biasing, electron tunneling is possible between the select gate and the floating gate and wherein the thickness of the second thin dielectric layer is such that with proper biasing, substantially no electron leakage is possible between the select gate and the control gate.
Claim 2
Dependent Claim
260 words
A Flash EEPROM cell structure comprising: a body of semiconductor material having a substrate of a first conductivity type, a source region and a drain region each of a second conductivity type, and a channel region of the first conductivity type extending between the source region and the drain region; a floating gate extending over a portion of the channel region with a thin insulator layer therebetween, the floating gate including one sidewall on one side thereof; a control gate overlying the floating gate with an insulator layer therebetween, so as to form a stack gate, the stack gate located proximately to the source region; and a non-self-aligned select gate insulated from the drain region and the stack gate, the select gate located proximately to the drain region and insulated from the sidewall of the floating gate with a first thin dielectric layer therebetween, and insulated from a sidewall of the control gate with a second thin dielectric layer therebetween, the select gate overlying a portion of the substrate and presenting a select gate channel length substantially along the channel region, the select gate also insulated from the portion of the substrate with a third thin dielectric layer therebetween, wherein the first thin dielectric layer is thinner than the second thin dielectric layer such that with proper biasing, electron tunneling is possible between the select gate and the floating gate and wherein the thickness of the second thin dielectric layer is such that with proper biasing, substantially no electron leakage is possible between the select gate and the control gate.
Claim 3
Dependent Claim
260 words
A Flash EEPROM cell structure comprising: a body of semiconductor material having a substrate of a first conductivity type, a source region and a drain region each of a second conductivity type, and a channel region of the first conductivity type extending between the source region and the drain region; a floating gate extending over a portion of the channel region with a thin insulator layer therebetween, the floating gate including one sidewall on one side thereof; a control gate overlying the floating gate with an insulator layer therebetween, so as to form a stack gate, the stack gate located proximately to the drain region; and a non-self-aligned select gate insulated from the source region and the stack gate, the select gate located proximately to the source region and insulated from the sidewall of the floating gate with a first thin dielectric layer therebetween, and insulated from a sidewall of the control gate with a second thin dielectric layer therebetween, the select gate overlying a portion of the substrate and presenting a select gate channel length substantially along the channel region, the select gate also insulated from the portion of the substrate with a third thin dielectric layer therebetween, wherein the first thin dielectric layer is thinner than the second thin dielectric layer such that with proper biasing, electron tunneling is possible between the select gate and the floating gate and wherein the thickness of the second thin dielectric layer is such that with proper biasing, substantially no electron leakage is possible between the select gate and the control gate.
Claim 4
Dependent Claim
260 words
A Flash EEPROM cell structure comprising: a body of semiconductor material having a substrate of a first conductivity type, a source region and a drain region each of a second conductivity type, and a channel region of the first conductivity type extending between the source region and the drain region; a floating gate extending over a portion of the channel region with a thin insulator layer therebetween, the floating gate including one sidewall on one side thereof; a control gate overlying the floating gate with an insulator layer therebetween, so as to form a stack gate, the stack gate located proximately to the drain region; and a non-self-aligned select gate insulated from the source region and the stack gate, the select gate located proximately to the source region and insulated from the sidewall of the floating gate with a first thin dielectric layer therebetween, and insulated from a sidewall of the control gate with a second thin dielectric layer therebetween, the select gate overlying a portion of the substrate and presenting a select gate channel length substantially along the channel region, the select gate also insulated from the portion of the substrate with a third thin dielectric layer therebetween, wherein the first thin dielectric layer is thinner than the second thin dielectric layer such that with proper biasing, electron tunneling is possible between the select gate and the floating gate and wherein the thickness of the second thin dielectric layer is such that with proper biasing, substantially no electron leakage is possible between the select gate and the control gate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-22 | 2003-05-24 | 2003-11-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-22 | 2007-05-24 | 2007-11-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-22 | 2011-05-24 | 2011-11-23 | $7700.00 | Window Closed / Lapsed |