Flash EEPROM with dual-sidewall gate

Claim 2

An EEPROM cell comprising a dual-gate transistor having a select gate, a floating gate and a control gate disposed on top of the floating gate, said gates being disposed above a channel and between a source and drain, said select gate being separated vertically from said channel by a gate oxide, said floating gate being separated vertically from said channel by a tunnel oxide and said control gate being separated vertically from said floating gate by a second layer of insulator; characterized in that: said select and floating gates are each formed from polysilicon sidewalls and are separated horizontally by a thin vertical insulating member; said select gate is disposed adjacent said source and said floating gate is disposed adjacent said drain; and said control gate extends over at least a portion of said select gate and said select gate is separated vertically from said control gate by a first predetermined dielectric layer and said floating gate is separated from said control gate by a second predetermined dielectric layer, said gate oxide and said first dielectric layer and said tunnel oxide and said second dielectric layer being related such that a predetermined program voltage on said control gate sufficient to cause electrons to tunnel through said tunnel oxide between said channel and said floating gate is insufficient to cause electrons to tunnel through said gate oxide.

Claim 3

An EEPROM cell according to claim 1, further characterized in that: said select gate has a vertical face abutting said vertical insulating member and a second face opposite said vertical face; said floating gate has a vertical face abutting said vertical insulating member and a second face opposite said vertical face; and said control gate extends over at least a predetermined portion of said floating gate.

Claim 4

An integrated circuit EEPROM comprising: input/output means for passing data into and out from said EEPROM; voltage generating means for generating a predetermined program voltage; voltage steering means for directing said program voltage along predetermined program paths in said circuit; and a memory array comprising: a set of dual-gate field effect transistor memory cells, each dual-gate transistor comprising a select gate, a control gate and a floating gate disposed above a channel and between said common source and a drain, said select gate being separated vertically from said channel by a gate oxide, said floating gate being separated vertically from said channel by a tunnel oxide and said control rate being separated vertically from said floating gate by a second layer of insulator, characterized in that: said select and floating gates are each formed from polysilicon sidewalls having a vertical side and are separated horizontally by a thin vertical insulating member adjacent said vertical side of said select and floating gates said select gate is disposed adjacent said source and said floating gate is disposed adjacent said drain; and said control gate extends over at least a portion of said select gate and said select gate is separated vertically from said control gate by a first predetermined dielectric layer and said floating gate is separated from said control gate by a second predetermined dielectric layer, said gate oxide and said first dielectric layer and said tunnel oxide and said second dielectric layer being related such that a predetermined program voltage on said control gate sufficient to cause electrons to tunnel through said tunnel oxide between said channel and said floating gate is insufficient to cause electrons to tunnel through said gate oxide.

Claim 5

An integrated circuit EEPROM comprising: input/output means for passing data into and out from said EEPROM; voltage generating means for generating a predetermined program voltage; voltage steering means for directing said program voltage along predetermined program paths in said circuit; and a memory array comprising: a set of dual-gate field effect transistor memory cells, each dual-gate transistor comprising a select gate, a control gate and a floating gate disposed above a channel and between said common source and a drain, said select gate being separated vertically from said channel by a gate oxide, said floating gate being separated vertically from said channel by a tunnel oxide and said control rate being separated vertically from said floating gate by a second layer of insulator, characterized in that: said select and floating gates are each formed from polysilicon sidewalls having a vertical side and are separated horizontally by a thin vertical insulating member adjacent said vertical side of said select and floating gates said select gate is disposed adjacent said source and said floating gate is disposed adjacent said drain; and said control gate extends over at least a portion of said select gate and said select gate is separated vertically from said control gate by a first predetermined dielectric layer and said floating gate is separated from said control gate by a second predetermined dielectric layer, said gate oxide and said first dielectric layer and said tunnel oxide and said second dielectric layer being related such that a predetermined program voltage on said control gate sufficient to cause electrons to tunnel through said tunnel oxide between said channel and said floating gate is insufficient to cause electrons to tunnel through said gate oxide.

Claim 6

An EEPROM according to claim 3, in which said cells are arranged in pairs of cells sharing a common source; and said select gates are disposed between said common source and said floating gates of said cells, whereby said cells are mirror images of one another.

Claim 7

An EEPROM according to claim 4, in which said drains of said cells are the bit lines of said EEPROM and a set of interconnection members connecting said control gates are the word lines of said EEPROM.

Claim 8

An integrated circuit EEPROM comprising: input/output means for passing data into and out from said EEPROM; voltage generating means for generating a predetermined program voltage; voltage steering means for directing said program voltage along predetermined program paths in said circuit; and a memory array comprising; a set of dual-gate field effect transistor memory cells, each dual-gate transistor comprising a select gate, a control gate and a floating gate disposed above a channel and between said common source and a drain, said select gate being separated vertically from said channel by a gate oxide, said floating gate being separated vertically from said channel by a tunnel oxide and said control gate being separated vertically from said floating gate by a second layer of insulator, characterized in that: said select and floating gates are each formed from polysilicon sidewalls having a vertical side and are separated horizontally by a thin vertical insulating member adjacent said vertical side of said select and floating gates; said bit lines extend throughout said memory array to a set of bit line contacts disposed above an insulating layer, hereby signals travelling along said bit lines pass through said set of bit lines contacts; and in which said bit line contacts are extensions of said select gates and formed from the same material.

Claim 9

An integrated circuit EEPROM comprising: input/output means for passing data into and out from said EEPROM; voltage generating means for generating a predetermined program voltage; voltage steering means for directing said program voltage along predetermined program paths in said circuit; and a memory array comprising; a set of dual-gate field effect transistor memory cells, each dual-gate transistor comprising a select gate, a control gate and a floating gate disposed above a channel and between said common source and a drain, said select gate being separated vertically from said channel by a gate oxide, said floating gate being separated vertically from said channel by a tunnel oxide and said control gate being separated vertically from said floating gate by a second layer of insulator, characterized in that: said select and floating gates are each formed from polysilicon sidewalls having a vertical side and are separated horizontally by a thin vertical insulating member adjacent said vertical side of said select and floating gates; said bit lines extend throughout said memory array to a set of bit line contacts disposed above an insulating layer, hereby signals travelling along said bit lines pass through said set of bit lines contacts; and in which said bit line contacts are extensions of said select gates and formed from the same material.