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EP0197284A2
Expired / Lapsed
EP
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Method of producing semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1986-02-28
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Granted: —
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Expires: 2006-02-28
Abstract
Abstract A method of producing a semiconductor memory device including the following steps, for example for providing a memory transistor (MTr) of a memory cell (e.g. of an EEPROM memory array) which includes also a selection transistor (STr). The memory transistor (MTr) has a floating gate (FG) and a tunnelable dielectric region (T) under the floating gate. The steps are:- forming a first mask or spacer layer (33 or 34) over the device substrate (31), forming an opening (35 or/and 36) in the first mask or spacer layer (33, 34), implanting ions into the substrate (31) via the opening (35, 36) to form an impurity region (37), forming a side wall layer (38, 48A), e.g. of oxidation-resistant material, to a selected width or thickness, on a side surface of the opening (35, 36) in the first mask or spacer layer (33, 34), forming the tunnelable dielectric region (T; 32) of a width determined by the selected width or thickness, using the side wall layer (38, 48A) as a second mask, and forming a gate part (FG, CG; 42, 43, 44) over the region (T).
Inventors
- 👤 Hideki Fujitsu Ltd Patent Dept. Arakawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 00:42
CPC Classifications
H; H10; H10B; H10B41/00; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/60; H10D30/68; H10D30/681; H10D30/683; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; H10D64/01328; H10D64/01332; H10D64/01334; H10D64/031; H10D64/035; Y; Y10; Y10S; Y10S148/00; Y10S148/106; Y10S148/114
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
115 words
A method of producing a semiconductor memory device comprising: a first step of forming a first mask on a substrate and forming an opening in said first mask; a second step of implanting impurity ions into said substrate through the opening in said first mask so as to form an impurity region; a third step of forming a side wall layer having a predetermined width on a side surface of the opening in said first mask; a fourth step of forming a tunnel region having a width determined by said predetermined width by using said side wall layer as a second mask; and a fifth step of forming a gate part on said tunnel region.
Claim 2
Independent Claim
115 words
A method of producing a semiconductor memory device comprising: a first step of forming a first mask on a substrate and forming an opening in said first mask; a second step of implanting impurity ions into said substrate through the opening in said first mask so as to form an impurity region; a third step of forming a side wall layer having a predetermined width on a side surface of the opening in said first mask; a fourth step of forming a tunnel region having a width determined by said predetermined width by using said side wall layer as a second mask; and a fifth step of forming a gate part on said tunnel region.
Claim 3
Dependent Claim
31 words
A method as claimed in claim 1 further comprising the step of forming a first dielectric layer on said substrate, wherein said first mask is formed on said first dielectric layer.
Claim 4
Dependent Claim
33 words
A method as claimed in claim 2 further comprising the step of forming a first conductor layer on said first dielectric layer, wherein said first mask is formed on said first conductor layer.
Claim 5
Dependent Claim
89 words
A method as claimed in claim 1, 2 or 3 in which said third step comprises a substep of forming an oxidation-resistant layer on said first mask which has the opening, and a substep of subjecting said oxidation-resistant layer to an etching process in a direction perpendicular to the substrate surface to etch and remove said oxidation-resistant layer so that an etching residue of said oxidation-resistant layer remains on the side surface of the opening in said first mask with said predetermined width to form said side wall layer.
Claim 6
Dependent Claim
37 words
A method as claimed in claim 4 further comprising the steps of selectively forming a gate dielectric layer on said substrate by using the remaining oxidation-resistant layer as said second mask and thereafter removing said second mask.
Claim 7
Dependent Claim
52 words
A method as claimed in claim 5 in which said fifth step comprises a substep of forming a second conductor layer on said gate layer, a substep of forming a second dielectric layer on said second conductor layer and a substep of forming a third conductor layer on said second dielectric layer.
Claim 8
Dependent Claim
27 words
A method as claimed in claim 1 in which said first mask is formed directly on said substrate and the opening is formed in said first mask.
Claim 9
Dependent Claim
86 words
A method as claimed in claim 7 in which said third step comprises a substep of forming an oxidation-resistant layer on said first mask which has the opening, and a substep of subjecting said oxidation-resistant layer to an etching process in a direction perpendicular to the substrate surface to etch and remove said oxidation-resistant layer so that an etching residue of said oxidation-resistant layer remains on the side surface of the opening in said first mask with said predetermined width to form said side wall layer.
Claim 10
Dependent Claim
63 words
A method as claimed in claim 8 further comprising the steps of selectively forming a gate dielectric layer on said substrate by using the remaining oxidation-resistant layer as said second mask, thereafter removing said second mask and forming a first dielectric layer on a part of said substrate which is exposed by the removal of said second mask to form said tunnel region.
Claim 11
Dependent Claim
53 words
A method as claimed in claim 9 in which said fifth step comprises a substep of forming a second conductor layer on said gate dielectric layer, a substep of forming a second dielectric layer on said second conductor layer and a substep of forming a third conductor layer on said second dielectric layer.
Claim 12
Dependent Claim
20 words
A method as claimed in claim 1 in which said side wall layer has a width of approximately 4000 A.
Claim 13
Dependent Claim
48 words
A method as claimed in claim 1 further comprising the step of forming a first dielectric layer on said substrate on which said first mask is formed, wherein said impurity ions are implanted into said substrate through said first dielectric layer from the opening in said first mask.
Claim 14
Independent Claim
292 words
A method of producing a semiconductor memory device comprising the steps of: forming on a semiconductor substrate a tunnel dielectric layer having such a thickness that electrons can pass through the tunnel dielectric layer; forming a polysilicon layer on said tunnel dielectric layer; forming on said polysilicon layer a mask layer for blocking impurity ions; forming an opening in said mask layer; implanting impurity ions into said silicon substrate through said polysilicon layer and said tunnel dielectric layer from the opening in said mask layer so as to form an impurity region which is aligned to the opening in said mask layer; forming an oxidation-resistant layer on said mask layer and inside of the opening in said mask layer; subjecting said oxidation-resistant layer to an etching process in a direction perpendicular to the substrate surface to etch and remove said oxidation-resistant layer so that an etching residue of said oxidation-resistant layer remains on a side surface of the opening in said mask layer with a predetermined width; patterning the remaining oxidation-resistant layer into a predetermined length so as to obtain an oxidation-resistant layer pattern; removing said mask layer; patterning said polysilicon layer by using said oxidation-resistant layer pattern as a mask so as to obtain a polysilicon layer pattern; forming a gate oxide layer having a thickness greater than the thickness of said tunnel dielectric layer on an exposed surface of said silicon substrate and a side surface of said polysilicon layer pattern by performing a selective oxidation process by using said oxidation-resistant layer pattern as a mask; removing said oxidation-resistant layer pattern; and forming a gate electrode which makes contact with a surface of said polysilicon layer pattern on said gate oxide layer including the surface of said polysilicon layer pattern.
Claim 15
Independent Claim
292 words
A method of producing a semiconductor memory device comprising the steps of: forming on a semiconductor substrate a tunnel dielectric layer having such a thickness that electrons can pass through the tunnel dielectric layer; forming a polysilicon layer on said tunnel dielectric layer; forming on said polysilicon layer a mask layer for blocking impurity ions; forming an opening in said mask layer; implanting impurity ions into said silicon substrate through said polysilicon layer and said tunnel dielectric layer from the opening in said mask layer so as to form an impurity region which is aligned to the opening in said mask layer; forming an oxidation-resistant layer on said mask layer and inside of the opening in said mask layer; subjecting said oxidation-resistant layer to an etching process in a direction perpendicular to the substrate surface to etch and remove said oxidation-resistant layer so that an etching residue of said oxidation-resistant layer remains on a side surface of the opening in said mask layer with a predetermined width; patterning the remaining oxidation-resistant layer into a predetermined length so as to obtain an oxidation-resistant layer pattern; removing said mask layer; patterning said polysilicon layer by using said oxidation-resistant layer pattern as a mask so as to obtain a polysilicon layer pattern; forming a gate oxide layer having a thickness greater than the thickness of said tunnel dielectric layer on an exposed surface of said silicon substrate and a side surface of said polysilicon layer pattern by performing a selective oxidation process by using said oxidation-resistant layer pattern as a mask; removing said oxidation-resistant layer pattern; and forming a gate electrode which makes contact with a surface of said polysilicon layer pattern on said gate oxide layer including the surface of said polysilicon layer pattern.
Claim 16
Independent Claim
163 words
A method of producing a semiconductor memory device comprising: a first step of forming a first spacer layer on a substrate; a second step of forming a first mask on said first spacer layer and forming an opening in said first mask; a third step of implanting impurity ions into said substrate through said first spacer layer from the opening in said first mask so as to form an impurity region; a fourth step of forming in said first spacer layer an opening corresponding to the opening in said first mask; a fifth step of removing said first mask; a sixth step of forming a side wall layer having a predetermined width on a side surface of the opening in said first spacer layer; a seventh step of forming a tunnel region having a width determined by said predetermined width by using said side wall layer as a second mask; and an eighth step of forming a gate part on said tunnel region.
Claim 17
Independent Claim
163 words
A method of producing a semiconductor memory device comprising: a first step of forming a first spacer layer on a substrate; a second step of forming a first mask on said first spacer layer and forming an opening in said first mask; a third step of implanting impurity ions into said substrate through said first spacer layer from the opening in said first mask so as to form an impurity region; a fourth step of forming in said first spacer layer an opening corresponding to the opening in said first mask; a fifth step of removing said first mask; a sixth step of forming a side wall layer having a predetermined width on a side surface of the opening in said first spacer layer; a seventh step of forming a tunnel region having a width determined by said predetermined width by using said side wall layer as a second mask; and an eighth step of forming a gate part on said tunnel region.
Claim 18
Dependent Claim
191 words
A method as claimed in claim 14 in which said sixth step comprises: a substep of forming an oxidation-resistant layer on said first spacer layer which has the opening; and a substep of subjecting said oxidation-resistant layer to an etching process in a direction perpendicular to the substrate surface to etch and remove said oxidation-resistant layer so that an etching residue of said oxidation-resistant layer remains on the side surface of the opening in said first spacer layer with said predetermined width to form said side wall layer, said seventh step comprises: a substep of forming a gate dielectric layer on said substrate by using the remaining oxidation-resistant layer as said second mask; a substep of thereafter removing said second mask; and a substep of forming a first dielectric layer on a part of said substrate which is exposed by the removal of said second mask, and said eighth step comprises: a substep of forming a first conductor layer on said gate dielectric layer; a substep of forming a second dielectric layer on said first conductor layer; and a substep of forming a second conductor layer on said second dielectric layer.
References Cited (Backward Citations)
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