Nonvolatile SNOS memory cell with induced capacitor

Claim 2

A nonvolatile semiconductor memory device comprising: a substrate of a first conductivity type; a region of a second conductivity type formed in a surface of said substrate; first gate means for generating an inversion layer in said substrate adjacent said region; first insulating means for insulating said first gate means from said substrate; second gate means for generating an inversion layer in said substrate contiguous with said inversion layer generated by said first gate means; charge retaining means for retaining a charge, said charge retaining means being disposed between said second gate means and said substrate; and second insulating means for insulating said charge retaining means from said substrate, said second insulating means selectively permitting transfer of a carrier.

Claim 3

The apparatus of claim 1 wherein said first conductivity type is a p-type conductivity and said second conductivity type is an n-type conductivity.

Claim 4

The apparatus of claim 1 wherein said first conductivity type is an n-type conductivity and said second conductivity type is a p-type conductivity.

Claim 5

The apparatus of claim 1 wherein said first and second gate means are polysilicon.

Claim 6

The apparatus of claim 1 wherein said second gate means is a metal.

Claim 7

The apparatus of claim 1 wherein said first and second insulating means are silicon dioxide.

Claim 8

The apparatus of claim 1 wherein said charge retaining means is silicon nitride.

Claim 9

The apparatus of claim 1 further comprising third insulating means for insulating said charge retaining means from said second gate means.

Claim 10

A nonvolatile semiconductor memory device comprising: a substrate of a first conductivity type; a region of a second conductivity type formed in a surface of said substrate; a first gate being disposed above a portion of said substrate adjacent to said region and generating an inversion layer therein; a first oxide layer being disposed between said surface of said substrate and said first gate; a second gate being disposed contiguous to said first gate to generate an inversion layer in said substrate substantially contiguous with the inversion layer generated by the first gate; a second oxide layer being disposed between said substrate and said second gate; and nitride layer for retaining electrical charge disposed between said second oxide layer and said second gate.

Claim 11

A nonvolatile semiconductor memory device comprising: a substrate of a first conductivity type; a region of a second conductivity type formed in a surface of said substrate; a first gate being disposed above a portion of said substrate adjacent to said region and generating an inversion layer therein; a first oxide layer being disposed between said surface of said substrate and said first gate; a second gate being disposed contiguous to said first gate to generate an inversion layer in said substrate substantially contiguous with the inversion layer generated by the first gate; a second oxide layer being disposed between said substrate and said second gate; and nitride layer for retaining electrical charge disposed between said second oxide layer and said second gate.

Claim 13

The apparatus of claim 9 wherein said first conductivity type is an n-type conductivity and said second conductivity type is a p-type conductivity.

Claim 14

The apparatus of claim 9 wherein said first and second gates are polysilicon.

Claim 15

The apparatus of claim 9 wherein said second gate is a metal.

Claim 16

The apparatus of claim 9 wherein said first and second oxide layers are silicon dioxide.

Claim 17

The apparatus of claim 9 wherein said nitride layer is silicon nitride.

Claim 18

The apparatus of claim 9 further comprising a third oxide layer disposed between said nitride layer and said second gate.

Claim 19

A silicon-nitride-oxide-silicon-type nonvolatile memory cell, comprising a silicon substrate having a drain region therein extending to a major surface of said substrate, an oxide layer overlying and in contact with a portion of said major surface of said substrate substantially up to a boundary with said drain region, a nitride layer having an edge substantially parallel to said boundary and overlying and in contact with a portion of said oxide layer, said nitride layer capable of storing an electrical charge therein, gate means directly overlying said nitride layer and overlying and in contact with said oxide layer other than said portion thereof, said portion of said oxide layer underlying said nitride layer being substantially thinner than the remainder of said oxide layer to allow electron tunneling through said thinner portion between said substrate and said nitride layer, and bias means coupled to said gate means and said drain region for controllably changing the polarity of the total electrical charge on the nitride layer to selectively induce or not induce a capacitance between said substrate and an inversion layer created or not created in the surface of said substrate beneath said gate means according to said polarity of electrical charge on the nitride layer, whereby to enable storing information in said cell as the presence or absence of said capacitance.

Claim 20

A silicon-nitride-oxide-silicon-type nonvolatile memory cell, comprising a silicon substrate having a drain region therein extending to a major surface of said substrate, an oxide layer overlying and in contact with a portion of said major surface of said substrate substantially up to a boundary with said drain region, a nitride layer having an edge substantially parallel to said boundary and overlying and in contact with a portion of said oxide layer, said nitride layer capable of storing an electrical charge therein, gate means directly overlying said nitride layer and overlying and in contact with said oxide layer other than said portion thereof, said portion of said oxide layer underlying said nitride layer being substantially thinner than the remainder of said oxide layer to allow electron tunneling through said thinner portion between said substrate and said nitride layer, and bias means coupled to said gate means and said drain region for controllably changing the polarity of the total electrical charge on the nitride layer to selectively induce or not induce a capacitance between said substrate and an inversion layer created or not created in the surface of said substrate beneath said gate means according to said polarity of electrical charge on the nitride layer, whereby to enable storing information in said cell as the presence or absence of said capacitance.

Claim 21

The invention of claim 10, wherein said gate means includes a first electrically conductive gate layer overlying and in contact with said nitride layer, a second electrically conductive gate layer overlying and in contact with said oxide layer other than said portion thereof, said first and second electrically conductive gates electrically isolated from one another, and having an edge substantially adjoining an edge of the other which is substantially parallel to said boundary, whereby to create substantially contiguous inversion layers in said major surface of said substrate beneath said first and second gate layers according to said polarity of electrical charge on said nitride layer.

Claim 22

The invention according to claim 18, wherein said bias means includes a first contact electrically connected to said first gate layer, a second contact electrically connected to said second gate layer, a third contact electrically connected to said drain region, a fourth contact electrically connected to said substrate, and said contacts being arranged and adapted for respective connection of supply potentials thereto according to the desired said polarity of electrical charge on said nitride layer.