Nonvolatile semiconductor memory device

Claim 2

A nonvolatile semiconductor memory device including at least one memory cell formed on a semiconductor substrate of P-type conductivity, each said memory cell comprising: only one region of N-type conductivity formed exclusively for the memory cell in said semiconductor substrate, said region having a contact for controlling its potential; a first insulating layer formed on said substrate adjacent said N-type region, said first insulating layer including a thin portion over said substrate through which tunneling by carriers occurs; a first gate formed on said first insulating layer including on said thin portion and adjacent to said N-type region; a second gate formed above said first gate and insulated therefrom, said second gate having a contact for controlling its potential; and means for selectively writing electrons as stored data into said first gate by said tunneling through said thin portion of said insulating layer, for erasing said stored data and for reading said stored data, including a word electrode connected to said contact of said second gate and a bit electrode connected to said contact of said N-type region, wherein for said selective writing a first positive potential is applied to said word line and said bit electrode is provided with a predetermined one of ground potential and a respective positive voltage, for said erasing a negative potential is applied to said word electrode and a respective positive potential is supplied to said bit electrode, and for said reading a second positive potential is applied to said word line and said bit electrode is floated electrically; wherein said first gate is capable of being placed in charged and discharged states with respective depletion regions of different sizes in said substrate under said first gate as a result of the respective potentials being supplied to said contacts of said N-type region and second gate.

Claim 3

A device as set forth in claim 1, wherein said first gate is changed in both directions between said charged and discharged states by applying the respective potentials to said contacts of said N-type region and said second gate so as to cause said tunneling in both respective directions.

Claim 4

A device as set forth in claim 2, wherein said thin portion of said first insulating layer is approximately 100 to 120 Å thick silicon dioxide (SiO 2 ).

Claim 5

The device of claim 1, comprising means selectively connected to said bit electrode for discriminating between the currents that flow from said N-type region to the respective depletion regions corresponding to said charged and discharged states during said reading.

Claim 6

The device of claim 1, wherein said erasing occurs by tunneling of said electrons through said thin portion of said first insulating layer.

Claim 7

The device of claim 1, wherein, said second positive potential is less than said first positive potential.

Claim 8

A device as set forth in claim 1, further comprising a third gate above said semiconductor substrate and between said N-type region and said first gate, said third gate being insulated from said semiconductor substrate and from said first and second gates, said thin portion of said insulating film being adjacent said third gate and said third gate having a contact for controlling its potential to provide a channel under said third gate to control when said tunneling occurs.

Claim 9

A device as set forth in claim 7, wherein said third gate is composed of polycrystalline silicon.

Claim 10

The device of claim 7, comprising reading means for discriminating between the currents that flow between said N-type region and the respective depletion regions corresponding to said charged and discharged states when a voltage is applied to said contact of said second gate so as to increase each of said depletion region.

Claim 11

A nonvolatile semiconductor memory device including at least one memory cell formed on a semiconductor substrate of P-type conductivity, each said memory cell comprising: only one region of N-type conductivity formed exclusively for the memory cell in said semiconductor substrate, said region having a contact for controlling its potential; a first insulating layer formed on said substrate adjacent said single region, said firs insulating layer including a thin portion over said substrate through which tunneling by carriers occurs; a first gate formed on said first insulating layer including on said thin portion and adjacent to said N-type region; a second gate formed above said first gate and insulated therefrom, said second gate having a contact for controlling its potential; and means for selectively writing electrons as stored data into said first gate by said tunneling through said thin portion of said insulating layer, for erasing said stored data and for reading said stored data, including a word electrode connected to said contact of said second gate and a bit electrode connected to said contact of said N-type region, wherein for the selective writing a first positive potential is applied to said word line and said bit electrode is provided with a predetermined one of ground potential and a respective positive voltage, for said erasing ground potential is applied to said word electrode and a respective positive potential is supplied to said bit electrode, and for said reading a second positive potential is applied to said word electrode and said bit electrode is floated electrically; wherein said first gate is capable of being placed in charged and discharged states, with respective depletion regions of different sizes in said substrate under said first gate during said reading as a result of the respective potential supplied to said contact of said second gate; and wherein said thin portion of said first insulating layer is spaced apart from said N-type region, said first insulating layer having a thick portion adjacent to said N-type region, and said first gate is discharged for said erasing by applying the respective potentials to said semiconductor substrate and to said N-type region so as to cause avalanche breakdown, causing carriers to pass over a potential barrier of said thick portion of the first insulating layer to discharge said first gate.

Claim 12

A nonvolatile semiconductor memory device including at least one memory cell formed on a semiconductor substrate of P-type conductivity, each said memory cell comprising: only one region of N-type conductivity formed exclusively for the memory cell in said semiconductor substrate, said region having a contact for controlling its potential; a first insulating layer formed on said substrate adjacent said single region, said firs insulating layer including a thin portion over said substrate through which tunneling by carriers occurs; a first gate formed on said first insulating layer including on said thin portion and adjacent to said N-type region; a second gate formed above said first gate and insulated therefrom, said second gate having a contact for controlling its potential; and means for selectively writing electrons as stored data into said first gate by said tunneling through said thin portion of said insulating layer, for erasing said stored data and for reading said stored data, including a word electrode connected to said contact of said second gate and a bit electrode connected to said contact of said N-type region, wherein for the selective writing a first positive potential is applied to said word line and said bit electrode is provided with a predetermined one of ground potential and a respective positive voltage, for said erasing ground potential is applied to said word electrode and a respective positive potential is supplied to said bit electrode, and for said reading a second positive potential is applied to said word electrode and said bit electrode is floated electrically; wherein said first gate is capable of being placed in charged and discharged states, with respective depletion regions of different sizes in said substrate under said first gate during said reading as a result of the respective potential supplied to said contact of said second gate; and wherein said thin portion of said first insulating layer is spaced apart from said N-type region, said first insulating layer having a thick portion adjacent to said N-type region, and said first gate is discharged for said erasing by applying the respective potentials to said semiconductor substrate and to said N-type region so as to cause avalanche breakdown, causing carriers to pass over a potential barrier of said thick portion of the first insulating layer to discharge said first gate.

Claim 13

The device of claim 10, comprising means connected to said bit electrode for discriminating between the currents that flow from said single region to the respective depletion regions corresponding to said charged and discharged states during said reading.

Claim 14

A device as set forth in claim 1, wherein said P-type conductivity of said substrate is provided by a P-type well region in said semiconductor substrate, and said semiconductor substrate further comprises a semiconductor layer of N-type conductivity extending in common beneath said well region.

Claim 15

A device as set forth in claim 10 or 12, wherein the thin portion of said insulating layer is approximately 100 to 120 Å thick silicon dioxide (SiO 2 ) and the thick portion of said insulating layer is approximately 500 to 1200 Å thick silicon dioxide (SiO 2 ).

Claim 16

A device as set forth in claim 1 or 12, wherein said first and second gates are composed of polycrystalline silicon.

Claim 17

A device as set forth in claim 14, wherein said first gate is surrounded by thermally grown silicon dioxide (SiO 2 ).

Claim 18

The device of claim 6, wherein every portion of said second gate is separated from said well region by said first gate.

Claim 19

The device of claim 12 or 16, comprising means for discriminating between the respective currents that flow from said N-type region to the respective depletion region during said reading when said voltage is supplied to said contact of said second gate as compared to the respective current for the other state.

Claim 20

A nonvolatile semiconductor memory device including at least one memory cell formed on a semiconductor substrate of P-type conductivity, each said memory cell comprising: only one region of N-type conductivity formed exclusively for the memory cell in said semiconductor substrate, said region having a contact for controlling its potential; a first insulating layer formed on said substrate adjacent said N-type region, said first insulating layer including a thin portion over said substrate through which tunneling by carriers occurs; a first gate formed on said first insulating layer including on said thin portion and adjacent to said N-type region; a second gate formed above said first gate and insulated therefrom, said second gate having a contact for controlling its potential; a third gate above said semiconductor substrate and between said N-type region and said first gate, said third gate being insulated from said semiconductor substrate and from said first and second gates, said thin portion of said insulating film being adjacent said third gate and said third gate having a contact for controlling its potential to provide a channel under said third gate: a program electrode connected to said contact of said second gate, a word electrode connected to said contact of said third gate, and a bit electrode connected to said contact of said N-type region, means for selectively writing electrons as said carriers into said first gate, and for erasing and reading said charged and discharged states, wherein for the selective writing a first positive potential is supplied to said program electrode and said bit electrode is selectively grounded or supplied with a respective positive voltage, depending on whether said charged or discharged state is selected, and a respective positive voltage is supplied to said word electrode, for said erasing respective positive voltages are applied to said word and bit electrodes and said program electrode is grounded, and for said reading respective positive voltages are supplied to said program and word electrodes, while said bit electrode is electrically floated; and wherein said first gate is capable of being placed in charged and discharged states, with respective depletion regions of different sizes in said substrate under said first gate during said reading as a result of the potential supplied to said contact of said second gate.

Claim 21

A nonvolatile semiconductor memory device including at least one memory cell formed on a semiconductor substrate of P-type conductivity, each said memory cell comprising: only one region of N-type conductivity formed exclusively for the memory cell in said semiconductor substrate, said region having a contact for controlling its potential; a first insulating layer formed on said substrate adjacent said N-type region, said first insulating layer including a thin portion over said substrate through which tunneling by carriers occurs; a first gate formed on said first insulating layer including on said thin portion and adjacent to said N-type region; a second gate formed above said first gate and insulated therefrom, said second gate having a contact for controlling its potential; a third gate above said semiconductor substrate and between said N-type region and said first gate, said third gate being insulated from said semiconductor substrate and from said first and second gates, said thin portion of said insulating film being adjacent said third gate and said third gate having a contact for controlling its potential to provide a channel under said third gate: a program electrode connected to said contact of said second gate, a word electrode connected to said contact of said third gate, and a bit electrode connected to said contact of said N-type region, means for selectively writing electrons as said carriers into said first gate, and for erasing and reading said charged and discharged states, wherein for the selective writing a first positive potential is supplied to said program electrode and said bit electrode is selectively grounded or supplied with a respective positive voltage, depending on whether said charged or discharged state is selected, and a respective positive voltage is supplied to said word electrode, for said erasing respective positive voltages are applied to said word and bit electrodes and said program electrode is grounded, and for said reading respective positive voltages are supplied to said program and word electrodes, while said bit electrode is electrically floated; and wherein said first gate is capable of being placed in charged and discharged states, with respective depletion regions of different sizes in said substrate under said first gate during said reading as a result of the potential supplied to said contact of said second gate.