Charge coupled memory with storage sites

Claim 2

A charge coupled memory device comprising: a charge storage medium, an insulating layer covering the charge storage medium, a plurality of several discrete charge storage sites within the charge storage medium each formed by an associated electrode field plate disposed on the insulating layer, said electrode field plates being spaced along the insulating layer with each contiguous to at least two other field plates such that with appropriate electrical bias applied to at least two of said electrode field plates electrical charge can be made to pass controllably between selected charge storage sites and ultimately to a detection site, and detector means for detecting charge at the detection site, the invention characterized in that the insulating layer has at least 1016 deep charge carrier traps per cm.3 and bias means for applying a first voltage to the electrode field plates for transferring charge between charge storage sites and an encoding means for applying between certain of the electrode field plates and the storage medium a second voltage of a sufficient magnitude to cause conduction of carriers between the storage medium and the deep traps.

Claim 3

A charge coupled memory device comprising: a charge storage medium, a first insulating layer covering the charge storage medium, a plurality of several discrete charge storage sites within the charge storage medium, each formed by an associated electrode field plate disposed on said first insulating layer, said electrode field plates being spaced along the insulating layer with each contiguous to at least two other field plates such that with appropriate electrical bias applied to at least two of said electrode field plates electrical charge can be made to pass controllably between selected storage sites and ultimately to a detection site, and detector means for detecting the charge at the detection site, the invention characterized in that at least some of the charge storage sites additionally include a second insulating layer overlying the first insulating layer, thereby forming deep charge carrier traps at the interface between the first and second insulating layers, and electrode means for interconnecting the second insulating layer with the charge storage medium for causing charge to flow between the storage medium and the deep traps.

Claim 4

A charge coupled memory device comprising: a charge storage medium, a first insulating layer covering the charge storage medium, a plurality of several discrete charge storage sites within the charge storage medium, each formed by an associated electrode field plate disposed on said first insulating layer, said electrode field plates being spaced along the insulating layer with each contiguous to at least two other field plates such that with appropriate electrical bias applied to at least two of said electrode field plates electrical charge can be made to pass controllably between selected storage sites and ultimately to a detection site, and detector means for detecting the charge at the detection site, the invention characterized in that at least some of the charge storage sites additionally include a second insulating layer overlying the first insulating layer, thereby forming deep charge carrier traps at the interface between the first and second insulating layers, and electrode means for interconnecting the second insulating layer with the charge storage medium for causing charge to flow between the storage medium and the deep traps.

Claim 5

The charge coupled memory device of claim 2 further including bias means for applying a first voltage to the electrode field plates for transferring charge between charge coupled elements, and a second voltage across the second insulating layer for causing charge to flow between the storage medium and the deep traps.

Claim 6

A charge coupled memory device comprising an array of semiconductor, insulated-gate, field effect devices each having an MIS drain region and selected ones having a source region, a gate common to at least several devices, the drain regions of these several devices disposed side-by-side to form a charge coupled line, means for simultaneously biasing the common gate and the drain regions and means for sequentially biasing the drain regions of the charge coupled line to shift charge along the line.

Claim 7

A charge coupled memory device comprising an array of semiconductor, insulated-gate, field effect devices each having an MIS drain region and selected ones having a source region, a gate common to at least several devices, the drain regions of these several devices disposed side-by-side to form a charge coupled line, means for simultaneously biasing the common gate and the drain regions and means for sequentially biasing the drain regions of the charge coupled line to shift charge along the line.

Claim 8

The memory device of claim 4 in which the selected source regions are p-n junctions.

Claim 9

The memory device of claim 4 in which the semiconductor and insulator of the MIS drain regions are silicon and SiO2 respectively.

Claim 10

A charge coupled memory device comprising an array of semiconductor, insulated-gate, field effect devices each having an MIS drain region and selected ones having a common gate, a source region common to at least several devices, the drain regions of these several devices disposed side-by-side to form a charge coupled line, means for simultaneously biasing the common gate and the drain regions and means for sequentially biasing the drain regions of the charge coupled line to shift charge along the line.

Claim 11

A charge coupled memory device comprising an array of semiconductor, insulated-gate, field effect devices each having an MIS drain region and selected ones having a common gate, a source region common to at least several devices, the drain regions of these several devices disposed side-by-side to form a charge coupled line, means for simultaneously biasing the common gate and the drain regions and means for sequentially biasing the drain regions of the charge coupled line to shift charge along the line.

Claim 12

The memory device of claim 7 in which the common source region comprises a p-n junction.

Claim 13

The memory device of claim 7 in which the semiconductor and insulator of the MIS drain regions are silicon and SiO2 respectively.

Claim 14

A charge coupled memory device comprising: a charge storage medium, a first insulating layer overlying the charge storage medium, a plurality of discrete memory plates positioned on the first insulating layer, said memory plates composed of a material capable of storing electrical charge, a second insulating layer covering at least the memory plates, the second layer having a thickness of at least twice the thickness of the first insulating layer, a plurality of several discrete drive electrodes positioned sequentially on said second insulating layer over the memory plates so as to form a plurality of several semiconductor-insulator-conductor-insulator-conductor charge storage memory elements, at least one charge coupled transfer element associated with each charge storage memory element so as to allow for transfer of charge sequentially between said charge storage memory elements and charge coupled transfer elements, means for reading the storage capacity of the charge storage memory elements comprising means for accumulating charge in each memory storage element in proportion to its storage capacity and a detection site located adjacent to one of said elements for detecting charge transferred from that element.

Claim 15

A charge coupled memory device comprising: a charge storage medium, a first insulating layer overlying the charge storage medium, a plurality of discrete memory plates positioned on the first insulating layer, said memory plates composed of a material capable of storing electrical charge, a second insulating layer covering at least the memory plates, the second layer having a thickness of at least twice the thickness of the first insulating layer, a plurality of several discrete drive electrodes positioned sequentially on said second insulating layer over the memory plates so as to form a plurality of several semiconductor-insulator-conductor-insulator-conductor charge storage memory elements, at least one charge coupled transfer element associated with each charge storage memory element so as to allow for transfer of charge sequentially between said charge storage memory elements and charge coupled transfer elements, means for reading the storage capacity of the charge storage memory elements comprising means for accumulating charge in each memory storage element in proportion to its storage capacity and a detection site located adjacent to one of said elements for detecting charge transferred from that element.

Claim 16

The charge coupled memory device of claim 10 further including: electrical means for interconnecting selected drive electrodes and the charge storage medium so that charge stored in the charge storage medium can be transferred to the memory plates, thereby selectively adjusting the storage capacity of the charge storage memory elements.

Claim 17

The device of claim 10 in which the means for transferring the charge comprises a three wire sequential drive system and each storage location comprises two conventional charge transfer coupled elements (without memory) and one charge storage memory element.

Claim 18

The device of claim 10 in which the means for accumulating charge in the charge storage memory elements is a means for effecting a time delay in the operation of the device so as to allow thermally generated charge to accumulate in each memory storage element to its equilibrium value.

Claim 19

The device of claim 10 which the means for accumulating charge in the charge storage memory elements includes a means for biasing the memory storage elements at a voltage sufficient to cause avalanching.

Claim 20

The device of claim 10 in which the means for accumulating charge in the charge storage memory elements comprises a lift source incident on the semiconductor substrate for creating free charge carriers.

Claim 21

The device of claim 10 in which the means for accumulating charge in the charge storage memory elements comprises means for biasing the memory elements at a first voltage for accumulating free charge at a rapid rate and means for reducing the bias to a second lower voltage for transferring the resulting accumulated charge.

Claim 22

A charge coupled memory device comprising: a charge storage medium, a first insulating layer covering the charge storage medium, a plurality of several discrete charge storage sites within the charge storage medium each formed by an associated electrode field plate disposed on said first insulating layer, said electrode field plates being spaced along the insulating layer with each contiguous to at least two other field plates such that with appropriate electrical bias applied sequentially to at least two of said electrical field plates electrical charge can be made to pass controllably between selected storage sites and ultimately to a detection site, and detector means for detecting the charge at the detection site, the invention characterized in that certain of the charge storage sites additionally include charge storage memory plates interposed between the first insulating layer and the charge storage medium, said memory plates being insulated from the charge storage medium by a second insulating layer having a transverse conduction of no more than half that of the first insulating layer.

Claim 23

A charge coupled memory device comprising: a charge storage medium, a first insulating layer covering the charge storage medium, a plurality of several discrete charge storage sites within the charge storage medium each formed by an associated electrode field plate disposed on said first insulating layer, said electrode field plates being spaced along the insulating layer with each contiguous to at least two other field plates such that with appropriate electrical bias applied sequentially to at least two of said electrical field plates electrical charge can be made to pass controllably between selected storage sites and ultimately to a detection site, and detector means for detecting the charge at the detection site, the invention characterized in that certain of the charge storage sites additionally include charge storage memory plates interposed between the first insulating layer and the charge storage medium, said memory plates being insulated from the charge storage medium by a second insulating layer having a transverse conduction of no more than half that of the first insulating layer.

Claim 24

The device of claim 17 further including means for applying a first voltage between selected drive electrodes and the said body, the voltage having a value sufficient to cause conduction of charge through said first insulating layer between the body and the memory plate but not through the second insulating layer, and means for applying a drive voltage to said drive electrodes in sequence to transfer charge storage elements, said drive voltage being substantially lower than the first voltage and insufficient to cause significant conduction of charge through the first insulating layer.

Claim 25

The device of claim 18 in which said body is silicon.

Claim 26

The device of claim 19 in which the first and second layers are SiO2.

Claim 27

The device of claim 20 in which the memory plates are metal.

Claim 28

The device of claim 20 in which the memory plates are semiconductor.

Claim 29

A charge coupled memory device comprising: a charge storage medium, an insulating layer covering the charge storage medium, a plurality of several discrete charge storage sites within the charge storage medium each formed by an associated electrode field plate disposed on the insulating layer, said electrode field plates being spaced along the insulating layer with eaCh contiguous to at lest two other field plates such that with appropriate electrical bias applied to at least two of said electrode field plates electrical charge can be made to pass controllably between selected charge storage sites and ultimately to a detection site, and detector means for detecting charge at the detection site the invention characterized in that the storage capacities of selected storage sites are adjusted to one of at least two predetermined values so that when the charge carriers accumulate in these storage sites to the storage capacity and are then transferred to the detection site a predetermined signal output is obtained.

Claim 30

A charge coupled memory device comprising: a charge storage medium, an insulating layer covering the charge storage medium, a plurality of several discrete charge storage sites within the charge storage medium each formed by an associated electrode field plate disposed on the insulating layer, said electrode field plates being spaced along the insulating layer with eaCh contiguous to at lest two other field plates such that with appropriate electrical bias applied to at least two of said electrode field plates electrical charge can be made to pass controllably between selected charge storage sites and ultimately to a detection site, and detector means for detecting charge at the detection site the invention characterized in that the storage capacities of selected storage sites are adjusted to one of at least two predetermined values so that when the charge carriers accumulate in these storage sites to the storage capacity and are then transferred to the detection site a predetermined signal output is obtained.

Claim 31

The device of claim 23 in which the storage capacity of selected sites is impermanently fixed by storage of a predetermined amount of fixed charge at these sites.

Claim 32

The device of claim 24 further including means for adjusting the amount of fixed charge stored.

Claim 33

The device of claim 23 in which the storage capacity of selected sites is fixed with a predetermined electrical capacitance.

Claim 34

The device of claim 26 in which the storage sites comprises MIS devices.

Claim 35

The device of claim 27 in which the electrical capacitance of selective sites is permanently fixed by providing insulating layers of varying thickness.

Claim 36

The device of claim 27 in which the electrical capacitance of selected sites is permanently fixed by proving metal layers with different work functions.

Claim 37

The device of claim 27 in which the insulating layer comprises an electrostrictive material and the electrical capacitance of selected sites is temporarily fixed by adjusting the thickness of the electrostrictive material at those sites.