US4813018A
Expired / Lapsed
US
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Nonvolatile semiconductor memory device
Assignee: Mitsubishi Electric Corp
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Filing: 1987-11-25
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Granted: 1989-03-14
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Expires: 2007-11-25
Abstract
Abstract A nonvolatile semiconductor memory device comprises a random access memory (RAM) and an electrically programmable and erasable read only memory (EEPROM). Since a capacitance (106) is formed between a control gate (103) and a drain (102) of a memory transistor, and a source of the memory transistor is rendered to be floating in the RAM write and read operation and in the EEPROM write operation and is supplied with a finite potential in EEPROM read operation, the operation of nonvolatile memory is achieved. A sense amplifier (15, 16) is amplified the potential difference between a bit line (BL) and a control gate line (CGL) is both memory operation and latches the input data in both write operation, such that the potential of the BL and the CGL are determined low or high potential. Besides in the EEPROM write operation, after latching the input data in the sense amplifier, a nonvolatile program is started such that a BL or a CGL is pumped up to program voltage (15-20 V). In the EEPROM read operation, a BL and a CGL are pre-changed in a different potential (BL<CGL) after equalizing in a same potential (BL=CGL), then the source of memory transistor is supplied with a fininte potential. Therefore, when the EEPROM transistor is conductive, is programmed "0", a BL is pre-charged more than a CGL potential (BL>CGL). After that, the sense amplifier is activated and the EEPROM data is read out.
Inventors
- 👤 Kazuo Kobayashi
- 👤 Yasushi Terada
- 👤 Takeshi Nakayama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:39
CPC Classifications
G; G11; G11C; G11C14/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
183 words
A nonvolatile semiconductor memory device having a plurality of memory cells (1-4) arranged in a matrix of rows and columns and each connected to a row selecting signal line (WL 1 ) and a bit line (BL 1 ) in which information can be electrically written and erased, each of said memory cells comprising a memory transistor (101) having a first electrode (102), a second electrode (103) and a third electrode (104), a capacitance (106) connected between the first electrode and the second electrode of said memory transistor, a first row selecting transistor (107) connected between the first electrode of said memory transistor and said bit line, a control gate line (CGL 1 ) for applying a control gate signal to the second electrode of said memory transistor, and a second row selecting transistor (108) connected between the second electrode of said memory transistor and said control gate line, a control transistor (109) connected to the third electrode of said memory transistor, and means (EER) for rendering said control transistor non-conductive and rendering the third electrode of said memory transistor to be floating.
Claim 2
Dependent Claim
183 words
A nonvolatile semiconductor memory device having a plurality of memory cells (1-4) arranged in a matrix of rows and columns and each connected to a row selecting signal line (WL 1 ) and a bit line (BL 1 ) in which information can be electrically written and erased, each of said memory cells comprising a memory transistor (101) having a first electrode (102), a second electrode (103) and a third electrode (104), a capacitance (106) connected between the first electrode and the second electrode of said memory transistor, a first row selecting transistor (107) connected between the first electrode of said memory transistor and said bit line, a control gate line (CGL 1 ) for applying a control gate signal to the second electrode of said memory transistor, and a second row selecting transistor (108) connected between the second electrode of said memory transistor and said control gate line, a control transistor (109) connected to the third electrode of said memory transistor, and means (EER) for rendering said control transistor non-conductive and rendering the third electrode of said memory transistor to be floating.
Claim 3
Dependent Claim
207 words
A nonvolatile semiconductor memory device having a plurality of memory cells in which information can be electrically written and erased arranged in a matrix, comprising column address decoder means (18) for decoding a column address signal externally applied, row address decoder means (17) for decoding a row address signal externally applied, a first data line (DL 1 ) for transferring input/output data, a second data line (DL 1 ) for transferring data which is complementary to said input/output data, means (42, 43) for causing said first and second data lines to be the same potential, sense amplifier means (15, 16) for differentially amplifying the potential difference between said first and second data lines, means (44-47) for applying said input/output data to said first and second data lines, charging means (11-14) for charging in advance said first and second data lines, a control signal line (EER) for applying a control signal to said memory cells, and high voltage applying means (5-10) for causing said first and second data lines and an output of said row address decoder means to be a high potential, said memory cell being connected to said first and second data lines, the output of said row address decoder means and said control signal line.
Claim 4
Dependent Claim
207 words
A nonvolatile semiconductor memory device having a plurality of memory cells in which information can be electrically written and erased arranged in a matrix, comprising column address decoder means (18) for decoding a column address signal externally applied, row address decoder means (17) for decoding a row address signal externally applied, a first data line (DL 1 ) for transferring input/output data, a second data line (DL 1 ) for transferring data which is complementary to said input/output data, means (42, 43) for causing said first and second data lines to be the same potential, sense amplifier means (15, 16) for differentially amplifying the potential difference between said first and second data lines, means (44-47) for applying said input/output data to said first and second data lines, charging means (11-14) for charging in advance said first and second data lines, a control signal line (EER) for applying a control signal to said memory cells, and high voltage applying means (5-10) for causing said first and second data lines and an output of said row address decoder means to be a high potential, said memory cell being connected to said first and second data lines, the output of said row address decoder means and said control signal line.
Claim 5
Dependent Claim
51 words
A nonvolatile semiconductor memory device according to claim 2, which further comprises means for charging said first and second data lines in advance to be different potentials and applying a potential to the third electrode of said nonvolatile memory transistor when information stored in said nonvolatile memory transistor is read out.
Claim 6
Dependent Claim
26 words
A nonvolatile semiconductor memory device according to claim 2, wherein said sense amplifier means comprises means for latching input data at the time of non-volatile programming.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-13 | 1992-09-12 | 1993-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-13 | 1996-09-12 | 1997-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-13 | 2000-09-12 | 2001-03-14 | $7700.00 | Window Closed / Lapsed |