US4658381A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bit line precharge on a column address change
Assignee: Motorola Solutions Inc
•
Filing: 1985-08-05
•
Granted: 1987-04-14
•
Expires: 2005-08-05
Abstract
Abstract A memory circuit has a plurality of bit line pairs and intersecting word lines with a memory cell located at each such intersection. A column address selects the bit line which is to be accessed and a row address selects the word line which is enabled. Memory cells along an enabled word line cause the bit lines to develop a voltage differential. In response to a change in the row address the bit lines are equalized and precharged. In response to a change in the column address, the bit lines are precharged without being equalized so that the developed voltage differential on the bit lines is maintained.
Inventors
- 👤 Paul A. Reed
- 👤 Stephen T. Flannagan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 13:27
CPC Classifications
G; G11; G11C; G11C7/00; G11C8/00; G11C8/18; G11C7/22
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
126 words
A memory circuit which has a plurality of bit line pairs which are selected by a column address, a plurality of word lines which are selected by a row address and a memory cell located at each intersection of the bit line pairs and word lines, the bit line pairs developing a voltage differential when a word line is enabled, comprising: a row detection means for detecting a row address change; column detection means for detecting a column address change; precharging means, coupled to the column detection means, for precharging the bit lines without equalizing the bit lines in response to a column address change; and equalizing means, coupled to the row detection means, for equalizing the bit lines in response to a row address change.
Claim 2
Dependent Claim
126 words
A memory circuit which has a plurality of bit line pairs which are selected by a column address, a plurality of word lines which are selected by a row address and a memory cell located at each intersection of the bit line pairs and word lines, the bit line pairs developing a voltage differential when a word line is enabled, comprising: a row detection means for detecting a row address change; column detection means for detecting a column address change; precharging means, coupled to the column detection means, for precharging the bit lines without equalizing the bit lines in response to a column address change; and equalizing means, coupled to the row detection means, for equalizing the bit lines in response to a row address change.
Claim 3
Dependent Claim
45 words
The memory circuit of claim 1 divided into a plurality of sub-arrays in which at least one is selected and the remainder deselected by the column or row address, wherein the bit lines in the deselected sub-arrays are equalized precharged in response to being deselected.
Claim 4
Dependent Claim
25 words
The memory circuit of claim 1 wherein the precharging means is further characterized as precharging the bit lines in response to a row address change.
Claim 5
Dependent Claim
99 words
In a memory circuit which has a plurality of bit line pairs which are selected by a column address and a plurality of word lines which are selected by a row address, the bit line pairs for developing a voltage differential when a word line is enabled, a memory cell located at each intersection of the bit line pairs and word lines, a method comprising the steps of: equalizing and precharging the bit lines in response to a row address change; and precharging the bit lines without equalizing the bit lines in response to a column only address change.
Claim 6
Dependent Claim
99 words
In a memory circuit which has a plurality of bit line pairs which are selected by a column address and a plurality of word lines which are selected by a row address, the bit line pairs for developing a voltage differential when a word line is enabled, a memory cell located at each intersection of the bit line pairs and word lines, a method comprising the steps of: equalizing and precharging the bit lines in response to a row address change; and precharging the bit lines without equalizing the bit lines in response to a column only address change.
Claim 7
Dependent Claim
146 words
A memory circuit which has a plurality of bit line pairs which are selected by a column address and a plurality of word lines which are selected by a row address, the bit line pairs for developing a voltage differential when a word line is enabled, a memory cell located at each intersection of the bit line pairs and word lines, comprising: row detection means for generating a row detection signal in response to detecting a row address transition; column detection means for generating a column detection signal in response to detecting a column address transition; logic means for generating a precharge signal in response to the generation of the row detection signal or the column detection signal; precharge means for precharging the bit lines in response to the precharge signal; and equalization means for equalizing the bit lines in response to the row detection signal.
Claim 8
Dependent Claim
146 words
A memory circuit which has a plurality of bit line pairs which are selected by a column address and a plurality of word lines which are selected by a row address, the bit line pairs for developing a voltage differential when a word line is enabled, a memory cell located at each intersection of the bit line pairs and word lines, comprising: row detection means for generating a row detection signal in response to detecting a row address transition; column detection means for generating a column detection signal in response to detecting a column address transition; logic means for generating a precharge signal in response to the generation of the row detection signal or the column detection signal; precharge means for precharging the bit lines in response to the precharge signal; and equalization means for equalizing the bit lines in response to the row detection signal.
Claim 9
Dependent Claim
92 words
The memory circuit of claim 5 wherein the precharge means comprises: a first transistor having a first current electrode coupled to a first bit line of a first bit line pair, a second current electrode coupled to a first power supply terminal, and a control electrode for receiving the precharge signal; and a second transistor having a first current electrode coupled to a second bit line of the first bit line pair, a second current electrode coupled to a first power supply terminal, and a control electrode for receiving the precharge signal.
Claim 10
Dependent Claim
57 words
The memory circuit of claim 6 wherein the equalization means comprises a third transistor having a first current electrode coupled to the first bit line of the first bit line pair, a second current electrode coupled to the second bit line of the first bit line pair, and a control electrode for receiving the row detection signal.
Claim 11
Dependent Claim
44 words
The memory circuit of claim 5 further characterized as having a column decoder which couples the selected bit line pair to a common data line pair, further comprising: equilibrating means for equalizing and precharging the common data line in response to the precharge signal.
Claim 12
Dependent Claim
22 words
The memory circuit of claim 8 further comprising disabling means for disabling the word lines in response to the row detection signal.
Claim 13
Dependent Claim
22 words
The memory circuit of claim 9 further comprising decoupling means for deselecting the bit lines in response to the column detection signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-04-13 | 1990-10-13 | 1991-04-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-04-13 | 1994-10-13 | 1995-04-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-04-13 | 1998-10-13 | 1999-04-14 | $7700.00 | Window Closed / Lapsed |